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ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 1 ? copyright 2011?2016 xilinx, inc. xilinx, the xilinx logo, zynq, virtex, artix, kintex, spartan, ise, vivado and other designa ted brands included herein are trademarks of xilinx in the united states and other countries. amba, amba designer, arm, cortex-a9, coresight, cortex, primecell, arm powered, and a rm connected partner are trademarks of arm ltd. all other trademarks are the property of their respective owners. introduction the zynq?-7000 all programmable socs are available in -3, -2, -1, and -1li speed grades, with -3 having the highest performance. the -1li devices can operate at either of two programmable logic (pl) v ccint /v ccbram voltages, 0.95v and 1.0v, and are screened for lower maximum static power. the speed specification of a -1li device is the same as the -1 speed grade. when operated at pl v ccint /v ccbram = 0.95v, the -1li static and dynamic power is reduced. zynq-7000 device dc and ac characteristics are specified in commercial, extended, industri al and expanded (q-temp) temperature ranges. except for the operating temperature range or unless otherwise noted, all the dc and ac electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -1 speed grade industrial device are the same as for a -1 speed grade commercial device). however, only selected speed grades and/or devices are available in the commercial, extended, industrial, or q-temp temperature ranges. all supply voltage and junction temperature specifications are representative of worst-ca se conditions. the parameters included are common to popular designs and typical applications. the available device/package co mbinations are outlined in: ? zynq-7000 all programmable soc overview ( ds190 ) ? xa zynq-7000 all programmable soc overview ( ds188 ) ? defense-grade zynq-7000q all programmable soc overview ( ds196 ) this zynq-7000 ap soc data sheet, which covers the specifications for the xc7z007s, xc7z012s, xc7z014s, XC7Z010, xa7z010, xc7z015, xc7z020, xa7z020, and xq7z020, complements the zynq-7000 ap soc documentation suite available on the xilinx website at www.xilinx.com/zynq . dc characteristics zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020): dc and ac switching characteristics ds187 (v1.19) october 3, 2016 product specification table 1: absolute maximum ratings (1) symbol description min max units processing system (ps) v ccpint ps internal logic supply voltage ?0.5 1.1 v v ccpaux ps auxiliary supply voltage ?0.5 2.0 v v ccpll ps pll supply ?0.5 2.0 v v cco_ddr ps ddr i/o supply voltage ?0.5 2.0 v v cco_mio (2) ps mio i/o supply voltage ?0.5 3.6 v v pref ps input reference voltage ?0.5 2.0 v v pin (2)(3)(4)(5) ps mio i/o input voltage ?0.40 v cco_mio +0.55 v ps ddr i/o input voltage ?0.55 v cco_ddr +0.55 v programmable logic (pl) v ccint pl internal supply voltage ?0.5 1.1 v v ccaux pl auxiliary supply voltage ?0.5 2.0 v v ccbram pl supply voltage for the block ram memories ?0.5 1.1 v v cco pl supply voltage for hr i/o banks ?0.5 3.6 v v ref input reference voltage ?0.5 2.0 v s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 2 v in (3)(4)(5) i/o input voltage for hr i/o banks ?0.40 v cco +0.55 v i/o input voltage (when v cco =3.3v) for v ref and differential i/o standards except tmds_33 (6) ?0.40 2.625 v v ccbatt key memory battery backup supply ?0.5 2.0 v gtp transceiver (xc7z015 only) v mgtavcc analog supply voltage for the gtp tran smitter and receiver circuits ?0.5 1.1 v v mgtavtt analog supply voltage for the gtp transmitter and receiver termination circuits ?0.5 1.32 v v mgtrefclk reference clock absolute input voltage ?0.5 1.32 v v in receiver (rxp/rxn) and transmitter (txp /txn) absolute input voltage ?0.5 1.26 v i dcin-float dc input current for receiver input pins dc coupled rx termination = floating ? 14 ma i dcin-mgtavtt dc input current for receiver input pins dc coupled rx termination = v mgtavtt ?12ma i dcin-gnd dc input current for receiver input pins dc coupled rx termination = gnd ? 6.5 ma i dcout-float dc output current for transmitter pins dc coupled rx termination = floating ? 14 ma i dcout-mgtavtt dc output current for transmitter pins dc coupled rx termination = v mgtavtt ?12ma xadc v ccadc xadc supply relative to gndadc ?0.5 2.0 v v refp xadc reference input relative to gndadc ?0.5 2.0 v temperature t stg storage temperature (ambient) ?65 150 c t sol maximum soldering temperature for pb/sn component bodies (7) ? +220 c maximum soldering temperature for pb-free component bodies (7) ? +260 c t j maximum junction temperature (7) ? +125 c notes: 1. stresses beyond those listed under absolute maximum ratings might cause permanent damage to the device. these are stress rati ngs only, and functional operation of the device at these or any other c onditions beyond those listed under operating conditions is not i mplied. exposure to absolute maximum ratings conditions for extended periods of time might affect device reliability. 2. applies to both mio supply banks v cco_mio0 and v cco_mio1 . 3. the lower absolute voltage specification always applies. 4. for i/o operation, refer to the 7 series fpgas selectio resources user guide ( ug471 ) or the zynq-7000 all programmable soc technical reference manual ( ug585 ). 5. the maximum limit applies to dc signals. for maximum undershoot and overshoot ac specifications, see table 4 . 6. see table 11 for tmds_33 specifications. 7. for soldering guidelines and thermal considerations, see the zynq-7000 all programmable soc packaging and pinout specification ( ug865 ). table 2: recommended operating conditions (1)(2) symbol description min typ max units ps v ccpint ps internal logic supply voltage 0.95 1.00 1.05 v v ccpaux ps auxiliary supply voltage 1.71 1.80 1.89 v v ccpll ps pll supply 1.71 1.80 1.89 v v cco_ddr ps ddr i/o supply voltage 1.14 ? 1.89 v v cco_mio (3) ps mio i/o supply voltage for mio banks 1.71 ? 3.465 v table 1: absolute maximum ratings (1) (cont?d) symbol description min max units s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 3 v pin (4) ps ddr and mio i/o input voltage ?0.20 ? v cco_ddr +0.20 v cco_mio +0.20 v pl v ccint (5) pl internal supply voltage 0.95 1.00 1.05 v pl -1li (0.95v) internal supply voltage 0.92 0.95 0.98 v v ccaux pl auxiliary supply voltage 1.71 1.80 1.89 v v ccbram (5) pl block ram supply voltage 0.95 1.00 1.05 v pl -1li (0.95v) block ram supply voltage 0.92 0.95 0.98 v v cco (6)(7) pl supply voltage for hr i/o banks 1.14 ? 3.465 v v in (4) i/o input voltage ?0.20 ? v cco +0.20 v i/o input voltage (when v cco = 3.3v) for v ref and differential i/o standards except tmds_33 (8) ?0.20 ? 2.625 v i in (9) maximum current through any (ps or pl) pin in a powered or unpowered bank when forward biasing the clamp diode ?? 10 ma v ccbatt (10) battery voltage 1.0 ? 1.89 v gtp transceiver (xc7z015 only) v mgtavcc (11) analog supply voltage for the gtp transmitt er and receiver circuits 0.97 1.0 1.03 v v mgtavtt (11) analog supply voltage for the gtp tr ansmitter and receiver termination circuits 1.17 1.2 1.23 v xadc v ccadc xadc supply relative to gndadc 1.71 1.80 1.89 v v refp externally supplied reference voltage 1.20 1.25 1.30 v temperature t j junction temperature operating rang e for commercial (c) temperature devices 0? 85 c junction temperature operating r ange for extended (e) temperature devices 0 ? 100 c junction temperature operating rang e for industrial (i) temperature devices ?40 ? 100 c junction temperature operating r ange for expanded (q) temperature devices ?40 ? 125 c notes: 1. all voltages are relative to ground. the pl and ps share a common ground. 2. for the design of the power distribution system consult the zynq-7000 all programmable soc pcb design guide ( ug933 ). 3. applies to both mio supply banks v cco_mio0 and v cco_mio1 . 4. the lower absolute voltage specification always applies. 5. v ccint and v ccbram should be connected to the same supply. 6. configuration data is retained even if v cco drops to 0v. 7. includes v cco of 1.2v, 1.5v, 1.8v, 2.5v, and 3.3v at 5%. 8. see table 11 for tmds_33 specifications. 9. a total of 200 ma per ps or pl bank should not be exceeded. 10. v ccbatt is required only when using bitstream encryp tion. if battery is not used, connect v ccbatt to either ground or v ccaux . 11. each voltage listed requires the filter circuit described in the 7 series fpgas gtp transceiver user guide ( ug482 ). table 2: recommended operating conditions (1)(2) (cont?d) symbol description min typ max units s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 4 table 3: dc characteristics over re commended operating conditions symbol description min typ (1) max units v drint data retention v ccint voltage (below which configuration data might be lost) 0.75 ? ? v v dri data retention v ccaux voltage (below which configuration data might be lost) 1.5 ? ? v i ref ps_ddr_vref 0/1, ps_ mio_vref, and v ref leakage current per pin ? ? 15 a i l input or output leakage current per pin (sample-tested) ? ? 15 a c in (2) pl die input capacitance at the pad ? ? 8 pf c pin (2) ps die input capacitance at the pad ? ? 8 pf i rpu pad pull-up (when selected) @ v in =0v, v cco = 3.3v 90 ? 330 a pad pull-up (when selected) @ v in =0v, v cco = 2.5v 68 ? 250 a pad pull-up (when selected) @ v in =0v, v cco = 1.8v 34 ? 220 a pad pull-up (when selected) @ v in =0v, v cco = 1.5v 23 ? 150 a pad pull-up (when selected) @ v in =0v, v cco = 1.2v 12 ? 120 a i rpd pad pull-down (when selected) @ v in = 3.3v 68 ? 330 a pad pull-down (when selected) @ v in = 1.8v 45 ? 180 a i ccadc analog supply current, analog circuits in powered up state ? ? 25 ma i batt (3) battery supply current ? ? 150 na r in_term (4) thevenin equivalent resistance of pr ogrammable input termination to v cco /2 (untuned_split_40) 28 40 55 thevenin equivalent resistance of pr ogrammable input termination to v cco /2 (untuned_split_50) 35 50 65 thevenin equivalent resistance of pr ogrammable input termination to v cco /2 (untuned_split_60) 44 60 83 n temperature diode ideality factor ? 1.010 ? ? r temperature diode series resistance ? 2 ? notes: 1. typical values are specified at nominal voltage, 25c. 2. this measurement represents the die capacitance at the pad, not including the package. 3. maximum value specified for worst case process at 25c. 4. termination resistance to a v cco /2 level. s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 5 table 4: v in maximum allowed ac voltage overshoot and u ndershoot for ps i/o and pl hr i/o banks (1)(2) ac voltage overshoot % of ui @?40c to 125c ac voltage undershoot % of ui @?40c to 125c v cco + 0.55 100 ?0.40 100 ?0.45 61.7 ?0.50 25.8 ?0.55 11.0 v cco + 0.60 46.6 ?0.60 4.77 v cco + 0.65 21.2 ?0.65 2.10 v cco + 0.70 9.75 ?0.70 0.94 v cco + 0.75 4.55 ?0.75 0.43 v cco + 0.80 2.15 ?0.80 0.20 v cco + 0.85 1.02 ?0.85 0.09 v cco + 0.90 0.49 ?0.90 0.04 v cco + 0.95 0.24 ?0.95 0.02 notes: 1. a total of 200 ma per bank should not be exceeded. 2. the peak voltage of the overshoot or undershoot, and the duration above v cco + 0.20v or below gnd ?0.20v, must not exceed the values in this table. table 5: typical quiescent supply current symbol descrip tion device speed grade units -3 -2 -1 -1li i ccpintq ps quiescent v ccpint supply current xc7z007s n/a 122 122 n/a ma xc7z012s n/a 122 122 n/a ma xc7z014s n/a 122 122 n/a ma XC7Z010 122 122 122 85 ma xc7z015 122 122 122 85 ma xc7z020 122 122 122 85 ma xa7z010 n/a n/a 122 n/a ma xa7z020 n/a n/a 122 n/a ma xq7z020 n/a 122 122 85 ma i ccpauxq ps quiescent v ccpaux supply current xc7z007s n/a 13 13 n/a ma xc7z012s n/a 13 13 n/a ma xc7z014s n/a 13 13 n/a ma XC7Z010 13 13 13 11 ma xc7z015 13 13 13 11 ma xc7z020 13 13 13 11 ma xa7z010 n/a n/a 13 n/a ma xa7z020 n/a n/a 13 n/a ma xq7z020 n/a 13 13 11 ma s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 6 i ccddrq ps quiescent v cco_ddr supply current xc7z007s n/a 4 4 n/a ma xc7z012s n/a 4 4 n/a ma xc7z014s n/a 4 4 n/a ma XC7Z010 4 4 4 4 ma xc7z015 4 4 4 4 ma xc7z020 4 4 4 4 ma xa7z010 n/a n/a 4 n/a ma xa7z020 n/a n/a 4 n/a ma xq7z020n/a444ma i ccintq pl quiescent v ccint supply current xc7z007s n/a 34 34 n/a ma xc7z012s n/a 77 77 n/a ma xc7z014s n/a 78 78 n/a ma XC7Z010 34 34 34 21/23 (4) ma xc7z015 77 77 77 47/53 (4) ma xc7z020 78 78 78 48/54 (4) ma xa7z010 n/a n/a 34 n/a ma xa7z020 n/a n/a 78 n/a ma xq7z020 n/a 78 78 48/54 (4) ma i ccauxq pl quiescent v ccaux supply current xc7z007s n/a 18 18 n/a ma xc7z012s n/a 35 35 n/a ma xc7z014s n/a 38 38 n/a ma XC7Z010 18 18 18 16 ma xc7z015 35 35 35 31 ma xc7z020 38 38 38 34 ma xa7z010 n/a n/a 18 n/a ma xa7z020 n/a n/a 38 n/a ma xq7z020 n/a 38 38 34 ma i ccoq pl quiescent v cco supply current xc7z007s n/a 3 3 n/a ma xc7z012s n/a 3 3 n/a ma xc7z014s n/a 3 3 n/a ma XC7Z010 3 3 3 3 ma xc7z015 3 3 3 3 ma xc7z020 3 3 3 3 ma xa7z010 n/a n/a 3 n/a ma xa7z020 n/a n/a 3 n/a ma xq7z020n/a333ma table 5: typical quiescent supply current (cont?d) symbol descrip tion device speed grade units -3 -2 -1 -1li s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 7 i ccbramq pl quiescent v ccbram supply current xc7z007s n/a 3 3 n/a ma xc7z012s n/a 4 4 n/a ma xc7z014s n/a 6 6 n/a ma XC7Z010 3 3 3 1/2 (4) ma xc7z015 4 4 4 2/2 (4) ma xc7z020 6 6 6 3/4 (4) ma xa7z010 n/a n/a 3 n/a ma xa7z020 n/a n/a 6 n/a ma xq7z020n/a663/4 (4) ma notes: 1. typical values are specified at nominal voltage, 85c junction temperatures (t j ) with single-ended selectio? resources. 2. typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all i/o pins are 3-state and floating. 3. the xilinx power estimator (xpe) spreadsheet tool (download at http://www.xilinx.com/power ) estimates operating current. when the required power-on current exceeds the estimated oper ating current, xpe can display the power-on current. 4. the first value is at 0.95v, and the second value is at 1.0v. table 5: typical quiescent supply current (cont?d) symbol descrip tion device speed grade units -3 -2 -1 -1li s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 8 ps power-on/off power supply sequencing the recommended power-on sequence is v ccpint , then v ccpaux and v ccpll together, then the ps v cco supplies (v cco_mio0 , v cco_mio1 , and v cco_ddr ) to achieve minimum current draw and ensure that the i/os are 3-stated at power-on. the ps_por_b input is required to be asserted to gnd during the powe r-on sequence until v ccpint , v ccpaux and v cco_mio0 have reached minimum operating levels to ensure ps efuse integrity. for additional information about ps_por_b timing requirements refer to resets . the recommended power-off sequence is the reverse of the power-on sequence. if v ccpaux , v ccpll , and the ps v cco supplies (v cco_mio0 , v cco_mio1 , and v cco_ddr ) have the same recommended voltage levels , then they can be powered by the same supply and ramped simultaneously. xilinx recommends powering v ccpll with the same supply as v ccpaux , with an optional ferrite bead filter. before v ccpint reaches 0.80v at least one of the four following conditions is required during the power-off stage: the ps_por_b input is asserted to gnd, the reference clock to the ps_clk input is disabled, v ccpaux is lower than 0.70v, or v cco_mio0 is lower than 0.90v. the condition must be held until v ccpint reaches 0.40v to ensu re ps efuse integrity. for v cco_mio0 and v cco_mio1 voltages of 3.3v: ? the voltage difference between v cco_mio0 /v cco_mio1 and v ccpaux must not exceed 2.625v for longer than t vcco2vccaux for each power-on/off cycle to ma intain device reliability levels. ?the t vcco2vccaux time can be allocated in any percentage between the power-on and power-off ramps. pl power-on/off power supply sequencing the recommended power-on se quence for the pl is v ccint , v ccbram , v ccaux , and v cco to achieve minimum current draw and ensure that the i/os are 3-stated at power-on. the recommended power-off se quence is the reverse of the power-on sequence. if v ccint and v ccbram have the same recommended voltage levels th en both can be powered by the same supply and ramped simultaneously. if v ccaux and v cco have the same recommended voltage le vels then both can be powered by the same supply and ra mped simultaneously. for v cco voltages of 3.3v in hr i/o banks and configuration bank 0: ? the voltage difference between v cco and v ccaux must not exceed 2.625v for longer than t vcco2vccaux for each power-on/off cycle to maintain device reliability levels. ?the t vcco2vccaux time can be allocated in any percentage between the power-on and power-off ramps. gtp transceivers (xc7z015 only) the recommended power-on sequence to achieve minimum cu rrent draw for the gtp transceivers (xc7z015 only) is v ccint , v mgtavcc , v mgtavtt or v mgtavcc , v ccint , v mgtavtt . both v mgtavcc and v ccint can be ramped simultaneously. the recommended power-off sequence is the reverse of the power-on sequence to achieve minimum current draw. if these recommended sequences are not met, current drawn from v mgtavtt can be higher than specifications during power-up and power-down. ?when v mgtavtt is powered before v mgtavcc and v mgtavtt ?v mgtavcc > 150 mv and v mgtavcc <0.7v, the v mgtavtt current draw can increase by 460 ma per transceiver during v mgtavcc ramp up. the duration of the current draw can be up to 0.3 x t mgtavcc (ramp time from gnd to 90% of v mgtavcc ). the reverse is true for power-down. ?when v mgtavtt is powered before v ccint and v mgtavtt ?v ccint > 150 mv and v ccint <0.7v, the v mgtavtt current draw can increase by 50 ma per transceiver during v ccint ramp up. the duration of th e current draw can be up to 0.3 x t vccint (ramp time from gnd to 90% of v ccint ). the reverse is tr ue for power-down. there is no recommended sequence for supplies not shown. ps?pl power sequencing the ps and pl power supplies are fully independent. ps power supplies (v ccpint , v ccpaux , v ccpll , v cco_ddr , v cco_mio0 , and v cco_mio1 ) can be powered before or after any pl power supplies. the ps and pl power regions are isolated to prevent damage. s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 9 power supply requirements table 6 shows the minimum current, in addition to i ccq , that is required by zynq-7000 devices for proper power-on and configuration. if the current minimums shown in table 5 and table 6 are met, the device powers on after all four pl supplies have passed through their power-on re set threshold voltages. the zynq-7000 device must not be configured until after v ccint is applied. once initialized and configured, use the x ilinx power estimator (xpe) spreadsheet tool (download at www.xilinx.com/power ) to estimate current drain on these supplies. table 6: power-on current for zynq-7000 devices device i ccpintmin i ccpauxmin i ccddrmin i ccintmin i ccauxmin i ccomin i ccbrammin units xc7z007s i ccpintq +70 i ccpauxq +40 i ccddrq +100ma per bank i ccintq +40 i ccauxq +60 i ccoq +90ma per bank i ccbramq +40 ma xc7z012s i ccpintq +70 i ccpauxq +40 i ccddrq +100ma per bank i ccintq +130 i ccauxq +60 i ccoq +90ma per bank i ccbramq +40 ma xc7z014s i ccpintq +70 i ccpauxq +40 i ccddrq +100ma per bank i ccintq +70 i ccauxq +60 i ccoq +90ma per bank i ccbramq +40 ma XC7Z010 xa7z010 i ccpintq +70 i ccpauxq +40 i ccddrq +100ma per bank i ccintq +40 i ccauxq +60 i ccoq +90ma per bank i ccbramq +40 ma xc7z015 i ccpintq +70 i ccpauxq +40 i ccddrq +100ma per bank i ccintq +130 i ccauxq +60 i ccoq +90ma per bank i ccbramq +40 ma xc7z020 xa7z020 xq7z020 i ccpintq +70 i ccpauxq +40 i ccddrq +100ma per bank i ccintq +70 i ccauxq +60 i ccoq +90ma per bank i ccbramq +40 ma table 7: power supply ramp time symbol description conditions min max units t vccpint ramp time from gnd to 90% of v ccpint 0.2 50 ms t vccpaux ramp time from gnd to 90% of v ccpaux 0.2 50 ms t vcco_ddr ramp time from gnd to 90% of v cco_ddr 0.2 50 ms t vcco_mio ramp time from gnd to 90% of v cco_mio 0.2 50 ms t vccint ramp time from gnd to 90% of v ccint 0.2 50 ms t vcco ramp time from gnd to 90% of v cco 0.2 50 ms t vccaux ramp time from gnd to 90% of v ccaux 0.2 50 ms t vccbram ramp time from gnd to 90% of v ccbram 0.2 50 ms t vcco2vccaux allowed time per power cycle for v cco ?v ccaux > 2.625v and v cco_mio ?v ccpaux > 2.625v t j = 125c (1) ?300 ms t j = 100c (1) ?500 t j = 85c (1) ?800 t mgtavcc ramp time from gnd to 90% of v mgtavcc 0.2 50 ms t mgtavtt ramp time from gnd to 90% of v mgtavtt 0.2 50 ms notes: 1. based on 240,000 power cycles with nominal v cco of 3.3v or 36,500 power cycles with worst case v cco of 3.465v. s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 10 dc input and output levels values for v il and v ih are recommended input voltages. values for i ol and i oh are guaranteed over the recommended operating conditions at the v ol and v oh test points. only selected standards are te sted. these are chosen to ensure that all standards meet their specific ations. the selected standards are tested at a minimum v cco with the respective v ol and v oh voltage levels shown. other standards are sample tested. ps i/o levels table 8: ps dc input and output levels (1) bank i/o standard v il v ih v ol v oh i ol i oh v, min v, max v, min v, max v, max v, min ma ma mio lvcmos18 ?0.300 35% v cco_mio 65% v cco_mio v cco_mio + 0.300 0.450 v cco_mio ? 0.450 8 ?8 mio lvcmos25 ?0.300 0.700 1.700 v cco_mio + 0.300 0.400 v cco_mio ? 0.400 8 ?8 mio lvcmos33 ?0.300 0.800 2.000 3.450 0.400 v cco_mio ? 0.400 8 ?8 mio hstl_i_18 ?0.300 v pref ? 0.100 v pref +0.100 v cco_mio + 0.300 0.400 v cco_mio ? 0.400 8 ?8 ddr sstl18_i ?0.300 v pref ? 0.125 v pref +0.125 v cco_ddr +0.300 v cco_ddr /2?0.470 v cco_ddr /2 + 0.470 8 ?8 ddr sstl15 ?0.300 v pref ? 0.100 v pref +0.100 v cco_ddr +0.300 v cco_ddr /2?0.175 v cco_ddr /2 + 0.175 13.0 ?13.0 ddr sstl135 ?0.300 v pref ? 0.090 v pref +0.090 v cco_ddr +0.300 v cco_ddr /2?0.150 v cco_ddr /2 + 0.150 13.0 ?13.0 ddr hsul_12 ?0.300 v pref ? 0.130 v pref +0.130 v cco_ddr + 0.300 20% v cco_ddr 80% v cco_ddr 0.1 ?0.1 notes: 1. tested according to relevant specifications. table 9: ps complementary differential dc input and output levels bank i/o standard v icm (1) v id (2) v ol (3) v oh (4) i ol i oh v, min v,typ v, max v,min v, max v, max v, min ma, max ma, min ddr diff_hsul_12 0.300 0.600 0.850 0.100 ? 20% v cco 80% v cco 0.100 ?0.100 ddr diff_sstl135 0.300 0.675 1.000 0.100 ? (v cco_ddr /2) ? 0.150 (v cco_ddr /2) + 0.150 13.0 ?13.0 ddr diff_sstl15 0.300 0.750 1.125 0.100 ? (v cco_ddr /2) ? 0.175 (v cco_ddr /2) + 0.175 13.0 ?13.0 ddr diff_sstl18_i 0.300 0.900 1.425 0.100 ? (v cco_ddr /2) ? 0.470 (v cco_ddr /2) + 0.470 8.00 ?8.00 notes: 1. v icm is the input common mode voltage. 2. v id is the input differential voltage (q?q ). 3. v ol is the single-ended low-output voltage. 4. v oh is the single-ended high-output voltage. s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 11 pl i/o levels table 10: selectio dc input and output levels (1)(2) i/o standard v il v ih v ol v oh i ol i oh v, min v, max v, min v, max v, max v, min ma ma hstl_i ?0.300 v ref ? 0.100 v ref + 0.100 v cco + 0.300 0.400 v cco ? 0.400 8.00 ?8.00 hstl_i_18 ?0.300 v ref ? 0.100 v ref + 0.100 v cco + 0.300 0.400 v cco ? 0.400 8.00 ?8.00 hstl_ii ?0.300 v ref ? 0.100 v ref + 0.100 v cco + 0.300 0.400 v cco ? 0.400 16.00 ?16.00 hstl_ii_18 ?0.300 v ref ? 0.100 v ref + 0.100 v cco + 0.300 0.400 v cco ? 0.400 16.00 ?16.00 hsul_12 ?0.300 v ref ? 0.130 v ref + 0.130 v cco +0.300 20%v cco 80% v cco 0.10 ?0.10 lvcmos12 ?0.300 35% v cco 65% v cco v cco + 0.300 0.400 v cco ?0.400 note 3 note 3 lvcmos15 ?0.300 35% v cco 65% v cco v cco +0.300 25%v cco 75% v cco note 4 note 4 lvcmos18 ?0.300 35% v cco 65% v cco v cco + 0.300 0.450 v cco ?0.450 note 5 note 5 lvcmos25 ?0.300 0.7 1.700 v cco + 0.300 0.400 v cco ?0.400 note 4 note 4 lvcmos33 ?0.300 0.8 2.000 3.450 0.400 v cco ?0.400 note 4 note 4 lvttl ?0.300 0.8 2.000 3.450 0.400 2.400 note 5 note 5 mobile_ddr ?0.300 20% v cco 80% v cco v cco +0.300 10%v cco 90% v cco 0.10 ?0.10 pci33_3 ?0.400 30% v cco 50% v cco v cco +0.500 10%v cco 90% v cco 1.50 ?0.50 sstl135 ?0.300 v ref ? 0.090 v ref + 0.090 v cco +0.300 v cco /2 ? 0.150 v cco /2 + 0.150 13.00 ?13.00 sstl135_r ?0.300 v ref ? 0.090 v ref + 0.090 v cco +0.300 v cco /2 ? 0.150 v cco /2 + 0.150 8.90 ?8.90 sstl15 ?0.300 v ref ? 0.100 v ref + 0.100 v cco +0.300 v cco /2 ? 0.175 v cco /2 + 0.175 13.00 ?13.00 sstl15_r ?0.300 v ref ? 0.100 v ref + 0.100 v cco +0.300 v cco /2 ? 0.175 v cco /2 + 0.175 8.90 ?8.90 sstl18_i ?0.300 v ref ? 0.125 v ref + 0.125 v cco +0.300 v cco /2 ? 0.470 v cco /2 + 0.470 8.00 ?8.00 sstl18_ii ?0.300 v ref ? 0.125 v ref + 0.125 v cco +0.300 v cco /2 ? 0.600 v cco /2 + 0.600 13.40 ?13.40 notes: 1. tested according to relevant specifications. 2. 3.3v and 2.5v standards are only supported in hr i/o banks. 3. supported drive strengths of 4, 8, or 12 ma in hr i/o banks. 4. supported drive strengths of 4, 8, 12, or 16 ma in hr i/o banks. 5. supported drive strengths of 4, 8, 12, 16, or 24 ma in hr i/o banks. 6. for detailed interface specific dc voltage levels, see the 7 series fpgas selectio resources user guide ( ug471 ). table 11: differential selectio dc input and output levels i/o standard v icm (1) v id (2) v ocm (3) v od (4) v, min v, typ v, max v, min v, typ v, max v, min v, typ v, max v, min v, typ v, max blvds_25 0.300 1.200 1.425 0.100 ? ? ? 1.250 ? note 5 mini_lvds_25 0.300 1.200 v ccaux 0.200 0.400 0.600 1.000 1.200 1.400 0.300 0.450 0.600 ppds_25 0.200 0.900 v ccaux 0.100 0.250 0.400 0.500 0.950 1.400 0.100 0.250 0.400 rsds_25 0.300 0.900 1.500 0.100 0.350 0. 600 1.000 1.200 1.400 0.100 0.350 0.600 tmds_33 2.700 2.965 3.230 0.150 0.675 1.200 v cco ?0.405 v cco ?0.300 v cco ?0.190 0.400 0.600 0.800 notes: 1. v icm is the input common mode voltage. 2. v id is the input differential voltage (q?q ). 3. v ocm is the output common mode voltage. 4. v od is the output differential voltage (q?q ). 5. v od for blvds will vary significantly depending on topology and loading. 6. lvds_25 is specified in table 13 . s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 12 lvds dc specifications (lvds_25) table 12: complementary differential selectio dc input and output levels i/o standard v icm (1) v id (2) v ol (3) v oh (4) i ol i oh v, min v,typ v, max v,min v, max v, max v, min ma, max ma, min diff_hstl_i 0.300 0.750 1.125 0.100 ? 0.400 v cco ?0.400 8.00 ?8.00 diff_hstl_i_18 0.300 0. 900 1.425 0.100 ? 0.400 v cco ?0.400 8.00 ?8.00 diff_hstl_ii 0.300 0.75 0 1.125 0.100 ? 0.400 v cco ?0.400 16.00 ?16.00 diff_hstl_ii_18 0.300 0.900 1.425 0.100 ? 0.400 v cco ?0.400 16.00 ?16.00 diff_hsul_12 0.300 0.600 0.850 0.100 ? 20% v cco 80% v cco 0.100 ?0.100 diff_mobile_ddr 0.300 0.900 1.425 0.100 ? 10% v cco 90% v cco 0.100 ?0.100 diff_sstl135 0.300 0.675 1.000 0.100 ? (v cco /2) ? 0.150 (v cco /2) + 0.150 13.0 ?13.0 diff_sstl135_r 0.300 0.675 1.000 0.100 ? (v cco /2) ? 0.150 (v cco /2) + 0.150 8.9 ?8.9 diff_sstl15 0.300 0.750 1.125 0.100 ? (v cco /2) ? 0.175 (v cco /2) + 0.175 13.0 ?13.0 diff_sstl15_r 0.300 0.750 1.125 0.100 ? (v cco /2) ? 0.175 (v cco /2) + 0.175 8.9 ?8.9 diff_sstl18_i 0.300 0.900 1.425 0.100 ? (v cco /2) ? 0.470 (v cco /2) + 0.470 8.00 ?8.00 diff_sstl18_ii 0.300 0.900 1.425 0.100 ? (v cco /2) ? 0.600 (v cco /2) + 0.600 13.4 ?13.4 notes: 1. v icm is the input common mode voltage. 2. v id is the input differential voltage (q?q ). 3. v ol is the single-ended low-output voltage. 4. v oh is the single-ended high-output voltage. table 13: lvds_25 dc specifications (1) symbol dc parameter conditions min typ max units v cco supply voltage 2.375 2.5 2.625 v v oh output high voltage for q and q r t = 100 across q and q signals ? ? 1.675 v v ol output low voltage for q and q r t = 100 across q and q signals 0.700 ? ? v v odiff differential output voltage: (q ? q ), q = high (q ?q), q =high r t = 100 across q and q signals 247 350 600 mv v ocm output common-mode voltage r t = 100 across q and q signals 1.00 1.25 1.425 v v idiff differential input voltage: (q ? q ), q = high (q ?q), q =high 100 350 600 mv v icm input common-mode voltage 0.3 1.2 1.500 v notes: 1. differential inputs for lvds_25 can be placed in banks with v cco levels that are different from the required level for outputs. consult the 7 series fpgas selectio resources user guide ( ug471 ) for more information. s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 13 ac switching characteristics all values represented in this data sheet are based on th e speed specifications in the ise? design suite 14.7 and vivado? design suite 2015.4 as outlined in table 14 . switching characteristics are specified on a per-speed-grade basis and can be designated as advance, preliminary, or production. each designatio n is defined as follows: advance product specification these specifications are based on simulations only and are typi cally available soon after device design specifications are frozen. although speed grades with this designation are considered relatively stab le and conservative, some under-reporting might still occur. preliminary produc t specification these specifications are based on complete es (engineering sample) silicon characterization. devices and speed grades with this designation are intended to give a be tter indication of the expected performanc e of production silicon. the probability of under-reporting delays is greatly reduced as compared to advance data. production product specification these specifications are released once enough production silicon of a particular device family member has been characterized to provide full correlation between specifications and devices over numerous production lots. there is no under-reporting of delays, and customers receive formal notification of any subs equent changes. typically, the slowest speed grades transition to production before faster speed grades. testing of ac switching characteristics internal timing parameters are derived from measuring inte rnal test patterns. all ac switching characteristics are representative of worst-case supply volt age and junction temperature conditions. for more specific, more precise, and worst-case guaranteed data , use the values reported by th e static timing analyzer and back-annotate to the simulation net list. unless othe rwise noted, values apply to all zynq-7000 devices. speed grade designations since individual family members are prod uced at different times, the migration from one category to another depends completely on the status of the fa brication process for each device. table 15 correlates the current st atus of each zynq-7000 device on a per speed grade basis. table 14: zynq-7000 all programmable soc speed specification version by device ise 14.7 vivado 2016.3 device 1.08 1.11 XC7Z010 and xc7z020 n/a 1.11 xc7z007s , xc7z012s , xc7z014s , and xc7z015 1.06 1.09 xa7z010 and xa7z020 1.06 1.10 xq7z020 table 15: zynq-7000 device speed grade designations device speed grade designations advance preliminary production xc7z007s -2e, -2i, -1c, -1i xc7z012s -2e, -2i, -1c, -1i xc7z014s -2e, -2i, -1c, -1i XC7Z010 -3e, -2e, -2i, -1c, -1i, -1li xc7z015 -3e, -2e, -2i, -1c, -1i, -1li s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 14 production silicon and software status in some cases, a particular family memb er (and speed grade) is released to production before a speed specification is released with the correct label (advance, preliminary, producti on). any labeling discrepancies are corrected in subsequent speed specification releases. table 16 lists the production released zynq-7000 device, speed grade, and the minimum co rresponding supported speed specification version and software revision s. the software and speed specifications listed are the minimum releases required for production. all subsequent releases of software and speed specifications are valid. selecting the correct speed grade and voltage in the vivado tools it is important to select the correct devi ce speed grade and voltage in the vivado to ols for the device that you are selecting. to select the -3, -2, or -1 (pl 1.0v) speed sp ecifications in the vivado tools, select the zynq-7000 , xa zynq-7000 , or defense grade zynq-7000 sub-family, and then select the part name that is the device name followed by the package name followed by the speed grade. for example, select the xc7z020clg484-3 part name for the xc7z020 device in the clg484 package and -3 speed grade. xc7z020 -3e, -2e, -2i, -1c, -1i, -1li xa7z010 -1i, -1q xa7z020 -1i, -1q xq7z020 -2i, -1i, -1q, -1li table 16: zynq-7000 device production software and speed specification release device speed grade designations -3e -2e -2i -1c -1i -1li -1q xc7z007s n/a vivado tools 2016.3 v1.11 n/a n/a xc7z012s n/a vivado tools 2016.3 v1.11 n/a n/a xc7z014s n/a vivado tools 2016.3 v1.11 n/a n/a XC7Z010 ise tools 14.5 v1.06 and vivado tools 2013.1 v1.06 ise tools 14.4 and the 14.4 device pack v1.05 and vivado tools 2013.1 v1.06 vivado tools 2014.4 v1.11 n/a xc7z015 vivado tools 2013.4 v1.09 vivado tools 2014.4 v1.11 n/a xc7z020 ise tools 14.5 v1.06 and vivado tools 2013.1 v1.06 ise tools 14.4 and the 14.4 device pack v1.05 and vivado tools 2013.1 v1.06 vivado tools 2014.4 v1.11 n/a xa7z010 n/a ise tools 14.5 v1.04 and vivado tools 2013.1 v1.04 n/a ise tools 14.6 v1.05 and vivado tools 2013.2 v1.05 xa7z020 n/a ise tools 14.5 v1.04 and vivado tools 2013.1 v1.04 n/a ise tools 14.6 v1.05 and vivado tools 2013.2 v1.05 xq7z020 n/a ise tools 14.6 v1.05 and vivado tools 2013.2 v1.05 n/a ise tools 14.6 v1.05 and vivado tools 2013.2 v1.05 vivado tools 2015.4 v1.10 ise tools 14.7 v1.06 and vivado tools 2013.3 v1.06 table 15: zynq-7000 device speed grade designations (cont?d) device speed grade designations advance preliminary production s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 15 to select the -1li (pl 0.95v) speed specif ications in the vivado tools, select the zynq-7000 sub-family and then select the part name that is the device name followed by an i followed by the package name followe d by the speed grade. for example, select the xc7z020iclg484-1l part name for the xc7z020 device in the clg 484 package and -1li (pl 0.95v) speed grade. the -1li (pl 0.95v) speed specificatio ns are not supported in the ise tools. a similar part naming co nvention applies to the speed specifications selection in the ise tools for supported devices. see table 16 for the subset of the zynq-7000 devices supported in the ise tools. ps performance characteristics for further design requirem ent details, refer to the zynq-7000 all programmable soc technical reference manual ( ug585 ). table 17: cpu clock domains performance symbol clock ratio description speed grade units -3 -2 -1c/-1i/-1li -1q f cpu_6x4x_621_max (1) 6:2:1 maximum cpu clock frequency 866 766 667 667 mhz f cpu_3x2x_621_max maximum cpu_3x clock frequency 433 383 333 333 mhz f cpu_2x_621_max maximum cpu_2x clock frequency 288 255 222 222 mhz f cpu_1x_621_max maximum cpu_1x clock frequency 144 127 111 111 mhz f cpu_6x4x_421_max (1) 4:2:1 maximum cpu clock frequency 710 600 533 533 mhz f cpu_3x2x_421_max maximum cpu_3x clock frequency 355 300 267 267 mhz f cpu_2x_421_max maximum cpu_2x clock frequency 355 300 267 267 mhz f cpu_1x_421_max maximum cpu_1x clock frequency 178 150 133 133 mhz notes: 1. the maximum frequency during bootrom execution is 500 mhz across all speed specifications. table 18: ps ddr clock domains performance (1) symbol description speed grade units -3 -2 -1c/-1i/-1li -1q f ddr3_max maximum ddr3 interface performance 1066 1066 1066 1066 mb/s f ddr3l_max maximum ddr3l interface performance 1066 1066 1066 1066 mb/s f ddr2_max maximum ddr2 interface performance 800 800 800 800 mb/s f lpddr2_max maximum lpddr2 interface performance 800 800 800 800 mb/s f ddrclk_2xmax maximum ddr_2x clock frequency 444 408 355 355 mhz notes: 1. all performance numbers apply to both internal and external v ref configurations. table 19: ps-pl interface performance symbol description min max units f emiogemclk emio gigabit ethernet controll er maximum frequency ? 125 mhz f emiosdclk emio sd controller maximum frequency ? 25 mhz f emiospiclk emio spi controller maximum frequency ? 25 mhz f emiojtagclk emio jtag controller maximum frequency ? 20 mhz f emiotraceclk emio trace controller maximum frequency ? 125 mhz f ftmclk fabric trace monitor maximum frequency ? 125 mhz f emiodmaclk dma maximum frequency ? 100 mhz f axi_max maximum axi interface performance ? 250 mhz s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 16 ps switching characteristics clocks resets the ps_por_b deassertion must meet the following requiremen ts to avoid coinciding with the secure lockdown window. figure 1 shows the timing relationsh ip between ps_por_b and th e last power supply ramp (v ccint , v ccbram , v ccaux , or v cco in bank 0). t slw minimum and maximum parameters define the beginnin g and end, respectively, of the secure lockdown window relative to the last pl power supply reaching 250 mv. the ps_por_b must not be deasserted within the secure lockdown window. table 20: system reference clock input requirements symbol description min typ max units t jtpsclk ps_clk rms clock jitter tolerance ? ? 0.5 % t dcpsclk ps_clk duty cycle 40 ? 60 % t rfpsclk ps_clk rise and fall time ? ? 6 ns f psclk ps_clk frequency 30 ? 60 mhz table 21: ps pll switching characteristics symbol description speed grade units -3 -2 -1c/-1i/-1li -1q t lock_pspll pll maximum lock time 60 60 60 60 s f pspll_max pll maximum output frequency 2000 1800 1600 1600 mhz f pspll_min pll minimum output frequency 780 780 780 780 mhz table 22: ps reset assertion timing requirements symbol description min typ max units t pspor required ps_por_b assertion time (1) 100 ? ? s t psrst required ps_srst_b assertion time 3 ? ? ps_clk clock cycles notes: 1. ps_por_b needs to be asserted low until t pspor after ps supply voltages reach minimum levels. x-ref target - figure 1 figure 1: ps_por_b and power supply ramp timing requirements p s _por_b l as t r a mping pl su pply s ec u re lockdown window do not de ass ert p s _por_b t s lw(min) t s lw(m a x) 250 mv d s 1 8 7_22_022015 s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 17 ps configuration ddr memory interfaces table 23: ps reset/power supply timing requirements symbol description ps_clk frequency (mhz) min max units t slw (1) 128 kb crc efuse disabled and pll enabled. default configuration 30 12 39 ms 33.33 12 40 ms 60 13 40 ms 128 kb crc efuse disabled and pll in bypass. 30 ?32 13 ms 33.33 ?27 13 ms 60 ?9 25 ms 128 kb crc efuse enabled and pll enabled. (2) 30 ?19 9 ms 33.33 ?16 12 ms 60 ?3 25 ms 128 kb crc efuse enabled and pll in bypass. (2) 30 ?830 ?788 ms 33.33 ?746 ?705 ms 60 ?408 ?374 ms notes: 1. valid for power supply ramp times of less than 6 ms. for ramp times longer than 6 ms, see the bootrom performance section of th e zynq-7000 all programmable soc technical reference manual ( ug585 ). 2. if any ps and pl power supplies are tied together, observe the ps_por_b assertion time requirement (t pspor ) in table 22 and its accompanying note. table 24: processor configuration access port switching characteristics symbol description min typ max units f pcapck maximum processor configuration access port (pcap) frequency ??100 mhz table 25: ddr3 interface switching characteristics (1066 mb/s) (1) symbol description min max units t dqvalid (2) input data valid window 450 ? ps t dqds (3) output dq to dqs skew 131 ? ps t dqdh (4) output dqs to dq skew 288 ? ps t dqss output clock to dqs skew ?0.11 0.09 t ck t cack (5) command/address output setup time with respect to clk 532 ? ps t ckca (6) command/address output hold time with respect to clk 637 ? ps notes: 1. recommended v cco_ddr =1.5v5%. 2. measurement is taken from v ref to v ref . 3. measurement is taken from either the rising edge of dq that crosses v ih (ac) or the falling edge of dq that crosses v il (ac) to v ref of dqs. 4. measurement is taken from either the rising edge of dq that crosses v il (dc) or the falling edge of dq that crosses v ih (dc) to v ref of dqs. 5. measurement is taken from either the rising edge of cmd/addr that crosses v ih (ac) or the falling edge of cmd/addr that crosses v il (ac) to v ref of clk. 6. measurement is taken from either the rising edge of cmd/addr that crosses v il (dc) or the falling edge of cmd/addr that crosses v ih (dc) to v ref of clk. s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 18 table 26: ddr3 interface switching characteristics (800 mb/s) (1) symbol description min max units t dqvalid (2) input data valid window 500 ? ps t dqds (3) output dq to dqs skew 232 ? ps t dqdh (4) output dqs to dq skew 401 ? ps t dqss output clock to dqs skew ?0.10 0.06 t ck t cack (5) command/address output setup time with respect to clk 722 ? ps t ckca (6) command/address output hold time with respect to clk 882 ? ps notes: 1. recommended v cco_ddr =1.5v5%. 2. measurement is taken from v ref to v ref . 3. measurement is taken from either the rising edge of dq that crosses v ih (ac) or the falling edge of dq that crosses v il (ac) to v ref of dqs. 4. measurement is taken from either the rising edge of dq that crosses v il (dc) or the falling edge of dq that crosses v ih (dc) to v ref of dqs. 5. measurement is taken from either the rising edge of cmd/addr that crosses v ih (ac) or the falling edge of cmd/addr that crosses v il (ac) to v ref of clk. 6. measurement is taken from either the rising edge of cmd/addr that crosses v il (dc) or the falling edge of cmd/addr that crosses v ih (dc) to v ref of clk. table 27: ddr3l interface switching characteristics (1066 mb/s) (1) symbol description min max units t dqvalid (2) input data valid window 450 ? ps t dqds (3) output dq to dqs skew 189 ? ps t dqdh (4) output dqs to dq skew 267 ? ps t dqss output clock to dqs skew ?0.13 0.04 t ck t cack (5) command/address output setup time with respect to clk 410 ? ps t ckca (6) command/address output hold time with respect to clk 629 ? ps notes: 1. recommended v cco_ddr = 1.35v 5%. 2. measurement is taken from v ref to v ref . 3. measurement is taken from either the rising edge of dq that crosses v ih (ac) or the falling edge of dq that crosses v il (ac) to v ref of dqs. 4. measurement is taken from either the rising edge of dq that crosses v il (dc) or the falling edge of dq that crosses v ih (dc) to v ref of dqs. 5. measurement is taken from either the rising edge of cmd/addr that crosses v ih (ac) or the falling edge of cmd/addr that crosses v il (ac) to v ref of clk. 6. measurement is taken from either the rising edge of cmd/addr that crosses v il (dc) or the falling edge of cmd/addr that crosses v ih (dc) to v ref of clk. table 28: ddr3l interface switching characteristics (800 mb/s) (1) symbol description min max units t dqvalid (2) input data valid window 500 ? ps t dqds (3) output dq to dqs skew 321 ? ps t dqdh (4) output dqs to dq skew 380 ? ps t dqss output clock to dqs skew ?0.12 0.04 t ck t cack (5) command/address output setup time with respect to clk 636 ? ps s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 19 t ckca (6) command/address output hold time with respect to clk 853 ? ps notes: 1. recommended v cco_ddr = 1.35v 5%. 2. measurement is taken from v ref to v ref . 3. measurement is taken from either the rising edge of dq that crosses v ih (ac) or the falling edge of dq that crosses v il (ac) to v ref of dqs. 4. measurement is taken from either the rising edge of dq that crosses v il (dc) or the falling edge of dq that crosses v ih (dc) to v ref of dqs. 5. measurement is taken from either the rising edge of cmd/addr that crosses v ih (ac) or the falling edge of cmd/addr that crosses v il (ac) to v ref of clk. 6. measurement is taken from either the rising edge of cmd/addr that crosses v il (dc) or the falling edge of cmd/addr that crosses v ih (dc) to v ref of clk. table 29: lpddr2 interface switching characteristics (800 mb/s) (1) symbol description min max units t dqvalid (2) input data valid window 500 ? ps t dqds (3) output dq to dqs skew 196 ? ps t dqdh (4) output dqs to dq skew 328 ? ps t dqss output clock to dqs skew 0.90 1.06 t ck t cack (5) command/address output setup time with respect to clk 202 ? ps t ckca (6) command/address output hold time with respect to clk 353 ? ps notes: 1. recommended v cco_ddr =1.2v5%. 2. measurement is taken from v ref to v ref . 3. measurement is taken from either the rising edge of dq that crosses v ih (ac) or the falling edge of dq that crosses v il (ac) to v ref of dqs. 4. measurement is taken from either the rising edge of dq that crosses v il (dc) or the falling edge of dq that crosses v ih (dc) to v ref of dqs. 5. measurement is taken from either the rising edge of cmd/addr that crosses v ih (ac) or the falling edge of cmd/addr that crosses v il (ac) to v ref of clk. 6. measurement is taken from either the rising edge of cmd/addr that crosses v il (dc) or the falling edge of cmd/addr that crosses v ih (dc) to v ref of clk. table 30: lpddr2 interface switching characteristics (400 mb/s) (1) symbol description min max units t dqvalid (2) input data valid window 500 ? ps t dqds (3) output dq to dqs skew 664 ? ps t dqdh (4) output dqs to dq skew 766 ? ps t dqss output clock to dqs skew 0.90 1.06 t ck t cack (5) command/address output setup time with respect to clk 731 ? ps t ckca (6) command/address output hold time with respect to clk 907 ? ps notes: 1. recommended v cco_ddr =1.2v5%. 2. measurement is taken from v ref to v ref . 3. measurement is taken from either the rising edge of dq that crosses v ih (ac) or the falling edge of dq that crosses v il (ac) to v ref of dqs. 4. measurement is taken from either the rising edge of dq that crosses v il (dc) or the falling edge of dq that crosses v ih (dc) to v ref of dqs. 5. measurement is taken from either the rising edge of cmd/addr that crosses v ih (ac) or the falling edge of cmd/addr that crosses v il (ac) to v ref of clk. 6. measurement is taken from either the rising edge of cmd/addr that crosses v il (dc) or the falling edge of cmd/addr that crosses v ih (dc) to v ref of clk. table 28: ddr3l interface switching characteristics (800 mb/s) (1) (cont?d) symbol description min max units s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 20 table 31: ddr2 interface switching characteristics (800 mb/s) (1) symbol description min max units t dqvalid (2) input data valid window 500 ? ps t dqds (3) output dq to dqs skew 147 ? ps t dqdh (4) output dqs to dq skew 376 ? ps t dqss output clock to dqs skew ?0.07 0.08 t ck t cack (5) command/address output setup time with respect to clk 732 ? ps t ckca (6) command/address output hold time with respect to clk 938 ? ps notes: 1. recommended v cco_ddr =1.8v5%. 2. measurement is taken from v ref to v ref . 3. measurement is taken from either the rising edge of dq that crosses v ih (ac) or the falling edge of dq that crosses v il (ac) to v ref of dqs. 4. measurement is taken from either the rising edge of dq that crosses v il (dc) or the falling edge of dq that crosses v ih (dc) to v ref of dqs. 5. measurement is taken from either the rising edge of cmd/addr that crosses v ih (ac) or the falling edge of cmd/addr that crosses v il (ac) to v ref of clk. 6. measurement is taken from either the rising edge of cmd/addr that crosses v il (dc) or the falling edge of cmd/addr that crosses v ih (dc) to v ref of clk. table 32: ddr2 interface switching characteristics (400 mb/s) (1) symbol description min max units t dqvalid (2) input data valid window 500 ? ps t dqds (3) output dq to dqs skew 385 ? ps t dqdh (4) output dqs to dq skew 662 ? ps t dqss output clock to dqs skew ?0.11 0.06 t ck t cack (5) command/address output setup time with respect to clk 1760 ? ps t ckca (6) command/address output hold time with respect to clk 1739 ? ps notes: 1. recommended v cco_ddr =1.8v5%. 2. measurement is taken from v ref to v ref . 3. measurement is taken from either the rising edge of dq that crosses v ih (ac) or the falling edge of dq that crosses v il (ac) to v ref of dqs. 4. measurement is taken from either the rising edge of dq that crosses v il (dc) or the falling edge of dq that crosses v ih (dc) to v ref of dqs. 5. measurement is taken from either the rising edge of cmd/addr that crosses v ih (ac) or the falling edge of cmd/addr that crosses v il (ac) to v ref of clk. 6. measurement is taken from either the rising edge of cmd/addr that crosses v il (dc) or the falling edge of cmd/addr that crosses v ih (dc) to v ref of clk. s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 21 x-ref target - figure 2 figure 2: ddr output timing diagram x-ref target - figure 3 figure 3: ddr input timing diagram write nop nop nop nop b a nk, col n d0 d1 d 3 t dqdh t dqd s t dqdh t dqd s t dq ss t ckca t cack t ckca t cack d s 1 8 7_01_01221 3 clk clk comm a nd addre ss dq s dq s dq d2 d0 d1 d2 d 3 t dqvalid clk clk dq s dq s dq d s 1 8 7_02_01221 3 s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 22 static memory controller table 33: smc interface delay characteristics (1)(2) symbol description min max units t nanddout nand_io output delay from last register to pad 4.12 6.45 ns t nandale nand_ale output delay from last register to pad 5.08 6.33 ns t nandcle nand_cle output delay from last register to pad 4.87 6.40 ns t nandwe nand_we_b output delay from last register to pad 4.69 5.89 ns t nandre nand_re_b output delay from last register to pad 5.12 6.44 ns t nandce nand_ce_b output delay from last register to pad 4.68 5.89 ns t nanddin nand_io setup time and input delay fr om pad to first register 1.48 3.09 ns t nandbusy nand_busy setup time and input delay from pad to first register 2.48 3.33 ns t srama sram_a output delay from last register to pad 3.94 5.73 ns t sramdout sram_dq output delay from last register to pad 4.66 6.45 ns t sramce sram_ce output delay from last register to pad 4.57 5.95 ns t sramoe sram_oe_b output delay from last register to pad 4.79 6.13 ns t srambls sram_bls_b output delay from last register to pad 5.25 6.74 ns t sramwe sram_we_b output delay from last register to pad 5.12 6.48 ns t sramdin sram_dq setup time and input delay fr om pad to first register 1.93 3.05 ns t sramwait sram_wait setup time and input delay from pad to first register 2.26 3.15 ns f smc_ref_clk smc reference clock frequency ? 100 mhz notes: 1. all parameters do not include the package flight time and register controlled delays. 2. refer to the arm? primecell? static memory controller (pl35 0 series) technical reference manual for more smc timing details. s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 23 quad-spi interfaces table 34: quad-spi interface switching characteristics symbol description load conditions min max units feedback clock enabled t dcqspiclk1 quad-spi clock duty cycle all (1)(2) 44 56 % t qspicko1 data and slave select output delay 15 pf (1) ?0.10 (3) 2.30 ns 30 pf (2) ?1.00 3.80 t qspidck1 input data setup time 15 pf (1) 2.00 ? ns 30 pf (2) 3.30 ? t qspickd1 input data hold time 15 pf (1) 1.30 ? ns 30 pf (2) 1.50 ? t qspissclk1 slave select asserted to next clock edge all (1)(2) 1?f qspi_ref_clk cycle t qspiclkss1 clock edge to slave select deasserted all (1)(2) 1?f qspi_ref_clk cycle f qspiclk1 quad-spi device clock frequency 15 pf (1) ? 100 (4) mhz 30 pf (2) ?70 (4) feedback clock disabled t dcqspiclk2 quad-spi clock duty cycle all (1)(2) 44 56 % t qspicko2 data and slave select output delay 15 pf (1) ?0.10 3.80 ns 30 pf (2) ?1.00 3.80 ns t qspidck2 input data setup time all (1)(2) 6?ns t qspickd2 input data hold time all (1)(2) 12.5 ? ns t qspissclk2 slave select asserted to next clock edge all (1)(2) 1?f qspi_ref_clk cycle t qspiclkss2 clock edge to slave select deasserted all (1)(2) 1?f qspi_ref_clk cycle f qspiclk2 quad-spi device clock frequency all (1)(2) ?40mhz feedback clock enab led or disabled f qspi_ref_clk quad-spi reference clock frequency all (1)(2) ?200mhz notes: 1. test conditions: lvcmos33, slow slew rate, 8 ma drive strength , 15 pf loads, feedback clock pin has no load. quad-spi single sl ave select 4-bit i/o mode. 2. test conditions: lvcmos33, slow slew rate, 8 ma drive strength, 30 pf loads in 4-bit stacked i/o configuration, feedback clock pin has no load. quad-spi single slave select 4-bit i/o mode. 3. the t qspicko1 is an effective value. use it to compute the available memory device input setup and hold timing budgets based on the given device clock-out duty-cycle limits. 4. requires appropriate component selection/board design. s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 24 x-ref target - figure 4 figure 4: quad-spi interface (feedback clock enabled) timing diagram x-ref target - figure 5 figure 5: quad-spi interface (feedback clock disabled) timing diagram q s pi{1,0}_ ss _b q s pi_ s clk_out cpol = 0 q s pi{1,0}_io_[ 3 ,0] q s pi_ s clk_out cpol = 1 d s 1 8 7_0 3 _110515 t q s picko1 t q s pi ss clk1 t q s pi ss clk1 t q s piclk ss 1 t q s piclk ss 1 t q s pidck1 t q s pickd1 out1 out0 inn-2 inn-1 inn out0 out1 inn-1 q s pi{1,0}_ ss _b q s pi_ s clk_out (cpol = 0) q s pi_ s clk_out (cpol = 1) q s pi{0,1}_io_[ 3 :0] t q s pickd2 t q s pidck2 t q s picko2 t q s piclk ss 2 t q s pi ss clk2 t q s piclk ss 2 t q s pi ss clk2 inn d s 1 8 7_04_110515 s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 25 ulpi interfaces table 35: ulpi interface clock receiving mode switching characteristics (1)(2) symbol description min typ max units t ulpidck input setup to ulpi clock, all inputs 3.00 ? ? ns t ulpickd input hold to ulpi clock, all inputs 1.00 ? ? ns t ulpicko ulpi clock to output vali d, all outputs 1.70 ? 8.86 ns f ulpiclk ulpi device clock frequency ? 60 ? mhz notes: 1. test conditions: lvcmos33, slow slew rate, 8 ma drive strength, 15 pf loads, 60 mhz device clock frequency. 2. all timing values assume an ideal external input clock. actual design system timing budgets should account for additional ext ernal clock jitter. x-ref target - figure 6 figure 6: ulpi interface timing diagram t ulpicko t ulpicko t ulpickd t ulpidck t ulpickd t ulpidck u s b{0,1}_ulpi_clk u s b{0,1}_ulpi_data[7:0] (inp u t) u s b{0,1}_ulpi_dir, u s b{0,1}_ulpi_nxt u s b{0,1}_ulpi_ s tp u s b{0,1}_ulpi_data[7:0] (o u tp u t) d s 1 8 7_05_02101 3 s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 26 rgmii and mdio interfaces table 36: rgmii and mdio interface switching characteristics (1)(2)(3) symbol description min typ max units t dcgetxclk transmit clock duty cycle 45 ? 55 % t gemtxcko rgmii_tx_d[3:0], rgmii_tx_ctl output clock to out time ?0.50 ? 0.50 ns t gemrxdck rgmii_rx_d[3:0], rgmii_rx_ctl input setup time 0.80 ? ? ns t gemrxckd rgmii_rx_d[3:0], rgmii_rx_ctl input hold time 0.80 ? ? ns t mdioclk mdc output clock period 400 ? ? ns t mdiockh mdc clock high time 160 ? ? ns t mdiockl mdc clock low time 160 ? ? ns t mdiodck mdio input data setup time 80 ? ? ns t mdiockd mdio input data hold time 0 ? ? ns t mdiocko mdio data output delay ?20 ? 170 ns f getxclk rgmii_tx_clk transmit clock frequency ? 125 ? mhz f gerxclk rgmii_rx_clk receive clock frequency ? 125 ? mhz f enet_ref_clk ethernet reference clock frequency ? 125 ? mhz notes: 1. test conditions: lvcmos25, fast slew rate, 8 ma drive strength, 15 pf loads. values in this table are specified during 1000 mb/s operation. 2. lvcmos25 slow slew rate and lvcmos33 are not supported. 3. all timing values assume an ideal external input clock. actual design system timing budgets should account for additional ext ernal clock jitter. x-ref target - figure 7 figure 7: rgmii interface timing diagram rgmii_tx_clk mdio_clk rgmii_rx_clk t gemtxcko t mdiockh t mdioclk t mdiockl t gemrxckd rgmii_tx_d[ 3 :0] rgmii_tx_ctl rgmii_rx_d[ 3 :0] rgmii_rx_ctl t gemrxdck t mdiockd mdio_io (inp u t) t mdiodck d s 1 8 7_06_02101 3 mdio_io (o u tp u t) t mdiocko s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 27 sd/sdio interfaces table 37: sd/sdio interface high speed mode switching characteristics (1) symbol description min typ max units t dcsdhsclk sd device clock duty cycle ? 50 ? % t sdhscko clock to output delay, all outputs 2.00 ? 12.00 ns t sdhsdck input setup time, all inputs 3.00 ? ? ns t sdhsckd input hold time, all inputs 1.05 ? ? ns f sd_ref_clk sd reference clock frequency ? ? 125 mhz f sdhsclk high speed mode sd device clock frequency 0 ? 50 mhz notes: 1. test conditions: lvcmos33, slow slew rate, 8 ma drive strength, 15 pf loads. x-ref target - figure 8 figure 8: sd/sdio interface high speed mode timing diagram table 38: sd/sdio interface switching characteristics (1) symbol description min typ max units t dcsdsclk sd device clock duty cycle ? 50 ? % t sdscko clock to output delay, all outputs 2.00 ? 12.00 ns t sdsdck input setup time, all inputs 4.00 ? ? ns t sdsckd input hold time, all inputs 3.00 ? ? ns f sd_ref_clk sd reference clock frequency ? ? 125 mhz f sdidclk clock frequency in identification mode ? ? 400 khz f sdsclk standard mode sd device clock frequency 0 ? 25 mhz notes: 1. test conditions: lvcmos33, slow slew rate, 8 ma drive strength, 15 pf loads. x-ref target - figure 9 figure 9: sd/sdio interface standard mode timing diagram t s dh s cko t s dh s ckd t s dh s dck s d{0,1}_clk s d{0,1}_data[ 3 :0], s d{0,1}_cmd (inp u t) s d{0,1}_data[ 3 :0], s d{0,1}_cmd (o u tp u t) d s 1 8 7_07_02101 3 d s 191_10 8 _0 3 011 3 t s d s cko t s d s ckd t s d s dck s d{0,1}_clk s d{0,1}_data[ 3 :0], s d{0,1}_cmd (inp u t) s d{0,1}_data[ 3 :0], s d{0,1}_cmd (o u tp u t) s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 28 i2c interfaces table 39: i2c fast mode interface switching characteristics (1) symbol description min typ max units t dci2cfclk i2c { 0,1}scl duty cycle ? 50 ? % t i2cfcko i2c { 0,1}sdao clock to out delay ? ? 900 ns t i2cfdck i2c { 0,1}sdai setup time 100 ? ? ns f i2cfclk i2c { 0,1}scl clock frequency ? ? 400 khz notes: 1. test conditions: lvcmos33, slow slew rate, 8 ma drive strength, 15 pf loads. x-ref target - figure 10 figure 10: i2c fast mode interface timing diagram table 40: i2c standard mode interface switching characteristics (1) symbol description min typ max units t dci2csclk i2c { 0,1}scl duty cycle ? 50 ? % t i2cscko i2c { 0,1}sdao clock to out delay ? ? 3450 ns t i2csdck i2c { 0,1}sdai setup time 250 ? ? ns f i2csclk i2c { 0,1}scl clock frequency ? ? 100 khz notes: 1. test conditions: lvcmos33, slow slew rate, 8 ma drive strength, 15 pf loads. x-ref target - figure 11 figure 11: i2c standard mode interface timing diagram t i2cfcko t i2cfdck d s 1 8 7_0 8 _02101 3 i2c{0,1} s cl i2c{0,1} s dai i2c{0,1} s dao t i2c s cko t i2c s dck d s 1 8 7_09_02101 3 i2c{0,1} s cl i2c{0,1} s dai i2c{0,1} s dao s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 29 spi interfaces table 41: spi master mode interface switching characteristics (1) symbol description min typ max units t dcmspiclk spi master mode clock duty cycle ? 50 ? % t mspidck input setup time for spi { 0,1}_miso 2.00 ? ? ns t mspickd input hold time for spi { 0,1}_miso 8.20 ? ? ns t mspicko output delay for spi { 0,1}_mosi and spi { 0,1}_ss ?3.10 ? 3.90 ns t mspissclk slave select asserted to first active clock edge 1 ? ? f spi_ref_clk cycles t mspiclkss last active clock edge to slave select deasserted 0.5 ? ? f spi_ref_clk cycles f mspiclk spi master mode device clock frequency ? ? 50.00 mhz f spi_ref_clk spi reference clock frequency ? ? 200.00 mhz notes: 1. test conditions: lvcmos33, slow slew rate, 8 ma drive strength, 15 pf loads. x-ref target - figure 12 figure 12: spi master (cpha = 0) interface timing diagram x-ref target - figure 13 figure 13: spi master (cpha = 1) interface timing diagram dn dn?1 dn?2 dn? 3 d0 dn dn?1 dn?2 t m s pickd t m s pidck t m s picko t m s piclk ss t m s pi ss clk s pi{0,1}_ ss s pi{0,1}_clk (cpol=0) s pi{0,1}_clk (cpol=1) s pi{0,1}_mo s i s pi{0,1}_mi s o d s 1 8 7_10_02101 3 dn dn?1 dn?2 dn? 3 d0 dn dn?1 dn?2 dn? 3 d0 t m s pickd t m s pidck t m s picko t m s piclk ss t m s pi ss clk s pi{0,1}_ ss s pi{0,1}_clk (cpol=0) s pi{0,1}_clk (cpol=1) s pi{0,1}_mo s i s pi{0,1}_mi s o d s 1 8 7_11_02101 3 s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 30 table 42: spi slave mode interface switching characteristics (1)(2) symbol description min max units t sspidck input setup time for spi { 0,1}_mosi and spi { 0,1}_ss 1 ? f spi_ref_clk cycles t sspickd input hold time for spi { 0,1}_mosi and spi { 0,1}_ss 1 ? f spi_ref_clk cycles t sspicko output delay for spi { 0,1}_miso 0 2.6 f spi_ref_clk cycles t sspissclk slave select asserted to first active clock edge 1 ? f spi_ref_clk cycles t sspiclkss last active clock edge to slave select deasserted 1 ? f spi_ref_clk cycles f sspiclk spi slave mode device clock frequency ? 25 mhz f spi_ref_clk spi reference clock frequency ? 200 mhz notes: 1. test conditions: lvcmos33, slow slew rate, 8 ma drive strength, 15 pf loads. 2. all timing values assume an ideal external input clock. actual design system timing budgets should account for additional ext ernal clock jitter. x-ref target - figure 14 figure 14: spi slave (cpha = 0) interface timing diagram x-ref target - figure 15 figure 15: spi slave (cpha = 1) interface timing diagram dn dn?1 dn?2 dn? 3 d0 dn dn?1 dn?2 dn? 3 d0 t ss picko t ss pickd t ss pidck t ss piclk ss t ss pi ss clk s pi{0,1}_ ss s pi{0,1}_clk (cpol=0) s pi{0,1}_clk (cpol=1) s pi{0,1}_mo s i s pi{0,1}_mi s o d s 1 8 7_12_02101 3 dn dn?1 dn?2 dn? 3 d0 dn dn?1 dn?2 dn? 3 d0 t ss picko t ss pickd t ss pidck t ss piclk ss t ss pi ss clk s pi{0,1}_ ss s pi{0,1}_clk (cpol=0) s pi{0,1}_clk (cpol=1) s pi{0,1}_mo s i s pi{0,1}_mi s o d s 1 8 7_1 3 _02101 3 s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 31 can interfaces pjtag interfaces uart interfaces table 43: can interface switching characteristics (1) symbol description min max units t pwcanrx minimum receive pulse width 1 ? s t pwcantx minimum transmit pulse width 1 ? s f can_ref_clk internally sourced can reference clock frequency ? 100 mhz externally sourced can reference clock frequency ? 40 mhz notes: 1. test conditions: lvcmos33, slow slew rate, 8 ma drive strength, 15 pf loads. table 44: pjtag interface (1)(2) symbol description min max units t pjtagdck pjtag input setup time 2.4 ? ns t pjtagckd pjtag input hold time 2.0 ? ns t pjtagcko pjtag clock to out delay ? 12.5 ns t pjtagclk pjtag clock frequency ? 20 mhz notes: 1. test conditions: lvcmos33, slow slew rate, 8 ma drive strength, 15 pf loads. 2. all timing values assume an ideal external input clock. actual design system timing budgets should account for additional ext ernal clock jitter. x-ref target - figure 16 figure 16: pjtag interface timing diagram table 45: uart interface switching characteristics (1) symbol description min max units baud txmax maximum transmit baud rate ? 1 mb/s baud rxmax maximum receive baud rate ? 1 mb/s f uart_ref_clk uart reference clock frequency ? 100 mhz notes: 1. test conditions: lvcmos33, slow slew rate, 8 ma drive strength, 15 pf loads. pjtagclk pjtagtm s , pjtagtdi pjtagtdo t pjtagdck t pjtagckd t pjtagcko d s 1 8 7_14_02101 3 s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 32 gpio interfaces trace interface triple timer counter interface watchdog timer table 46: gpio banks switching characteristics (1) symbol description min max units t pwgpioh input high pulse width 10 x 1/cpu1x ? s t pwgpiol input low pulse width 10 x 1/cpu1x ? s notes: 1. pulse width requirement for interrupt. x-ref target - figure 17 figure 17: gpio interface timing diagram table 47: trace interface switching characteristics (1) symbol description min max units t tcecko trace clock to output delay, all outputs ?1.4 1.5 ns t dctceclk trace clock duty cycle 40 60 % f tceclk trace clock frequency ? 80 mhz notes: 1. test conditions: lvcmos25, fast slew rate, 8 ma drive strength, 15 pf loads. table 48: triple timer counter interface switching characteristics (1) symbol description min max units t pwttcoclk triple timer counter output clock pulse width 2 x 1/cpu1x ? ns f ttcoclk triple timer counter output clock frequency ? cpu1x/4 mhz t ttciclkh triple timer counter input clock high pulse width 1.5 x 1/cpu1x ? ns t ttciclkl triple timer counter input clock low pulse width 1.5 x 1/cpu1x ? ns f ttciclk triple timer counter input clock frequency ? cpu1x/3 mhz notes: 1. all timing values assume an ideal external input clock. actual design system timing budgets should account for additional ext ernal clock jitter. table 49: watchdog timer switching characteristics symbol descripti on min max units f wdtclk (1) watchdog timer input clock frequency ? 10 mhz notes: 1. applies to external input clock through mio pin only. t pwgpiol t pwgpioh gpio d s 1 8 7_15_02101 3 s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 33 pl performance characteristics this section provides the performance ch aracteristics of some common functions and designs implemented in the pl. the numbers reported here are worst-case valu es; they have all been fully characterize d. these values are subject to the same guidelines as the ac switching characteristics, page 13 . table 50: pl networking applications interface performances description speed grade units -3 -2 -1c/-1i/-1li -1q sdr lvds transmitter (using oserdes; data_width = 4 to 8) 680 680 600 600 mb/s ddr lvds transmitter (using oserdes; data_width = 4 to 14) 1250 1250 950 950 mb/s sdr lvds receiver (sfi-4.1) (1) 680 680 600 600 mb/s ddr lvds receiver (spi-4.2) (1) 1250 1250 950 950 mb/s notes: 1. lvds receivers are typically bounded with certain applications where specific dynamic phase-alignment (dpa) algorithms domina te deterministic performance. table 51: maximum physical interface (phy) rate for memory interfaces ip available with the memory interface generator (1)(2) memory standard speed grade units -3 -2 -1c/-1i/-1li -1q 4:1 memory controllers ddr3 1066 (3) 800 800 667 mb/s ddr3l 800 800 667 n/a mb/s ddr2 800 800 667 533 mb/s 2:1 memory controllers ddr3 800 700 620 620 mb/s ddr3l 800 700 620 n/a mb/s ddr2 800 700 620 533 mb/s lpddr2 667 667 533 400 mb/s notes: 1. v ref tracking is required. for more information, see the zynq-7000 ap soc and 7 series devices memory interface solutions user guide ( ug586 ). 2. when using the internal v ref , the maximum data rate is 800 mb/s (400 mhz). 3. the maximum phy rate is 800 mb/s in bank 13 of the xc7z015, xc7z020, xa7z020, and xq7z020 devices. s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 34 pl switching characteristics iob pad input/output/3-state table 52 summarizes the values of standard-specific data input dela y adjustments, output delays terminating at pads (based on standard), and 3-state delays. ?t iopi is described as the delay from iob pad through the inpu t buffer to the i-pin of an iob pad. the delay varies depending on the capability of the selectio input buffer. ?t ioop is described as the delay from the o pin to the iob pad through the output buffer of an iob pad. the delay varies depending on the capability of the selectio output buffer. ?t iotp is described as the delay from the t pin to the iob pad through the output buffer of an iob pad, when 3-state is disabled. the delay varies depending on the selectio capability of the output buffer. in hr i/o banks, the in_term termination turn-on time is always faster than t iotp when the intermdisable pin is used. table 52: iob high range (hr) sw itching characteristics i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade -3 -2 -1c/-1i/ -1li -1q -3 -2 -1c/-1i/ -1li -1q -3 -2 -1c/-1i/ -1li -1q lvttl_s4 1.26 1.34 1.41 1.53 3.80 3. 93 4.18 4.18 3.82 3.96 4.20 4.20 ns lvttl_s8 1.26 1.34 1.41 1.53 3.54 3. 66 3.92 3.92 3.56 3.69 3.93 3.93 ns lvttl_s12 1.261.341.411.533.523.653.903.903.543.683.913.91 ns lvttl_s16 1.261.341.411.533.073.193.453.453.093.223.463.46 ns lvttl_s24 1.261.341.411.533.293.413.673.673.313.443.683.68 ns lvttl_f4 1.26 1.34 1.41 1.53 3.26 3. 38 3.64 3.64 3.28 3.41 3.65 3.65 ns lvttl_f8 1.26 1.34 1.41 1.53 2.74 2. 87 3.12 3.12 2.76 2.90 3.13 3.13 ns lvttl_f12 1.261.341.411.532.732.853.103.102.742.883.123.12 ns lvttl_f16 1.261.341.411.532.562.682.932.932.572.712.952.95 ns lvttl_f24 1.261.341.411.532.522.652.903.232.542.682.913.24 ns lvds_25 0.730.810.880.891.291.411.671.671.311.441.681.68 ns mini_lvds_25 0.73 0.81 0.88 0.89 1.27 1.40 1.65 1.65 1.29 1.43 1.66 1.66 ns blvds_25 0.73 0.81 0.88 0.88 1.84 1. 96 2.21 2.76 1.85 1.99 2.23 2.77 ns rsds_25 (point to point) 0.73 0.81 0.88 0.89 1.27 1.40 1. 65 1.65 1.29 1.43 1.66 1.66 ns ppds_25 0.73 0.81 0.88 0.89 1.29 1. 41 1.67 1.67 1.31 1.44 1.68 1.68 ns tmds_33 0.730.810.880.921.411.541.791.791.431.571.801.80 ns pci33_3 1.24 1.32 1.39 1.52 3.10 3.22 3.48 3.48 3.12 3.25 3.49 3.49 ns hsul_12_s 0.67 0.75 0.82 0.88 1.81 1. 93 2.18 2.18 1.82 1.96 2.20 2.20 ns hsul_12_f 0.67 0.75 0.82 0.88 1.29 1.41 1.67 1.67 1.31 1.44 1.68 1.68 ns diff_hsul_12_s 0.68 0.76 0.83 0.86 1. 81 1.93 2.18 2.18 1.82 1.96 2.20 2.20 ns diff_hsul_12_f 0.68 0.76 0.83 0.86 1. 29 1.41 1.67 1.67 1.31 1.44 1.68 1.68 ns mobile_ddr_s 0.760.840.910.911.681.802.062.061.701.832.072.07 ns mobile_ddr_f 0.760.840.910.911.381.511.761.761.401.541.771.77 ns diff_mobile_ddr_s 0.70 0.78 0.85 0.85 1.70 1.82 2.07 2.07 1.71 1.85 2.09 2.09 ns diff_mobile_ddr_f 0.70 0.78 0.85 0.85 1.45 1.57 1.82 1.82 1.46 1.60 1.84 1.84 ns hstl_i_s 0.67 0.75 0.82 0.86 1.62 1. 74 1.99 1.99 1.63 1.77 2.01 2.01 ns hstl_ii_s 0.65 0.73 0.80 0.86 1.41 1 .54 1.79 1.79 1.43 1.57 1.80 1.81 ns s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 35 hstl_i_18_s 0.67 0.75 0.82 0.88 1.29 1.41 1.67 1.67 1.31 1.44 1.68 1.68 ns hstl_ii_18_s 0.66 0.75 0.81 0.88 1.41 1.54 1.79 1.79 1.43 1.57 1.80 1.80 ns diff_hstl_i_s 0.68 0.76 0. 83 0.86 1.59 1.71 1.96 1. 96 1.60 1.74 1.98 1.98 ns diff_hstl_ii_s 0.68 0.76 0.83 0.86 1.5 11.631.881.881.521.661.901.90 ns diff_hstl_i_18_s 0.71 0.79 0.86 0.86 1.38 1.51 1.76 1. 76 1.40 1.54 1.77 1.77 ns diff_hstl_ii_18_s 0.70 0. 78 0.85 0.88 1.46 1.58 1.84 1.84 1.48 1.61 1.85 1.85 ns hstl_i_f 0.67 0.75 0.82 0.86 1.10 1. 22 1.48 1.49 1.12 1.25 1.49 1.51 ns hstl_ii_f 0.65 0.73 0.80 0.86 1.12 1 .24 1.49 1.49 1.13 1.27 1.51 1.51 ns hstl_i_18_f 0.67 0.75 0.82 0.88 1.13 1.26 1.51 1.54 1.15 1.29 1.52 1.56 ns hstl_ii_18_f 0.66 0.75 0.81 0.88 1.12 1.24 1.49 1.51 1.13 1.27 1.51 1.52 ns diff_hstl_i_f 0.68 0.76 0. 83 0.86 1.18 1.30 1.56 1. 56 1.20 1.33 1.57 1.57 ns diff_hstl_ii_f 0.68 0.76 0.83 0.86 1.2 11.331.591.591.231.361.601.60 ns diff_hstl_i_18_f 0.71 0.79 0.86 0.86 1.21 1.33 1.59 1. 59 1.23 1.36 1.60 1.60 ns diff_hstl_ii_18_f 0.70 0. 78 0.85 0.88 1.21 1.33 1.59 1.59 1.23 1.36 1.60 1.60 ns lvcmos33_s4 1.26 1.34 1.41 1.52 3.80 3.93 4.18 4.18 3.82 3.96 4.20 4.20 ns lvcmos33_s8 1.26 1.34 1.41 1.52 3.52 3.65 3.90 3.90 3.54 3.68 3.91 3.91 ns lvcmos33_s12 1.26 1.34 1.41 1.52 3.09 3.21 3.46 3.46 3.10 3.24 3.48 3.48 ns lvcmos33_s16 1.26 1.34 1.41 1.52 3.40 3.52 3.77 3.78 3.42 3.55 3.79 3.79 ns lvcmos33_f4 1.26 1.34 1.41 1.52 3.26 3.38 3.64 3.64 3.28 3.41 3.65 3.65 ns lvcmos33_f8 1.26 1.34 1.41 1.52 2.74 2.87 3.12 3.12 2.76 2.90 3.13 3.13 ns lvcmos33_f12 1.26 1.34 1.41 1.52 2.56 2.68 2.93 2.93 2.57 2.71 2.95 2.95 ns lvcmos33_f16 1.26 1.34 1.41 1.52 2.56 2.68 2.93 3.06 2.57 2.71 2.95 3.07 ns lvcmos25_s4 1.12 1.20 1.27 1.38 3.13 3.26 3.51 3.51 3.15 3.29 3.52 3.52 ns lvcmos25_s8 1.12 1.20 1.27 1.38 2.88 3.01 3.26 3.26 2.90 3.04 3.27 3.27 ns lvcmos25_s12 1.12 1.20 1.27 1.38 2.48 2.60 2.85 2.85 2.49 2.63 2.87 2.87 ns lvcmos25_s16 1.12 1.20 1.27 1.38 2.82 2.94 3.20 3.20 2.84 2.97 3.21 3.21 ns lvcmos25_f4 1.12 1.20 1.27 1.38 2.74 2.87 3.12 3.12 2.76 2.90 3.13 3.13 ns lvcmos25_f8 1.12 1.20 1.27 1.38 2.18 2.30 2.56 2.56 2.20 2.33 2.57 2.57 ns lvcmos25_f12 1.12 1.20 1.27 1.38 2.16 2.29 2.54 2.54 2.18 2.32 2.55 2.56 ns lvcmos25_f16 1.12 1.20 1.27 1.38 2.01 2.13 2.39 2.63 2.03 2.16 2.40 2.65 ns lvcmos18_s4 0.74 0.83 0.89 0.97 1.62 1.74 1.99 1.99 1.63 1.77 2.01 2.01 ns lvcmos18_s8 0.74 0.83 0.89 0.97 2.18 2.30 2.56 2.56 2.20 2.33 2.57 2.57 ns lvcmos18_s12 0.74 0.83 0.89 0.97 2.18 2.30 2.56 2.56 2.20 2.33 2.57 2.57 ns lvcmos18_s16 0.74 0.83 0.89 0.97 1.52 1.65 1.90 1.90 1.54 1.68 1.91 1.91 ns lvcmos18_s24 0.74 0.83 0.89 0.97 1.60 1.72 1.98 2.40 1.62 1.75 1.99 2.41 ns lvcmos18_f4 0.74 0.83 0.89 0.97 1.45 1.57 1.82 1.82 1.46 1.60 1.84 1.84 ns lvcmos18_f8 0.74 0.83 0.89 0.97 1.68 1.80 2.06 2.06 1.70 1.83 2.07 2.07 ns lvcmos18_f12 0.74 0.83 0.89 0.97 1.68 1.80 2.06 2.06 1.70 1.83 2.07 2.07 ns lvcmos18_f16 0.74 0.83 0.89 0.97 1.40 1.52 1.77 1.78 1.42 1.55 1.79 1.79 ns table 52: iob high range (hr) switching characteristics (cont?d) i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade -3 -2 -1c/-1i/ -1li -1q -3 -2 -1c/-1i/ -1li -1q -3 -2 -1c/-1i/ -1li -1q s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 36 table 53 specifies the values of t iotphz and t ioibufdisable . t iotphz is described as the delay from the t pin to the iob pad through the output buffer of an iob pad, when 3- state is enabled (i.e., a high impedance state). t ioibufdisable is described as the iob delay from ibufdisable to o output. in hr i/o banks, the internal in_term termination turn-off time is always faster than t iotphz when the intermdisable pin is used. lvcmos18_f24 0.74 0.83 0.89 0.97 1.34 1.46 1.71 2.28 1.35 1.49 1.73 2.29 ns lvcmos15_s4 0.77 0.86 0.93 0.96 2.05 2.18 2.43 2.43 2.07 2.21 2.45 2.45 ns lvcmos15_s8 0.77 0.86 0.93 0.96 2.09 2.21 2.46 2.46 2.10 2.24 2.48 2.48 ns lvcmos15_s12 0.77 0.86 0.93 0.96 1.59 1.71 1.96 1.96 1.60 1.74 1.98 1.98 ns lvcmos15_s16 0.77 0.86 0.93 0.96 1.59 1.71 1.96 1.96 1.60 1.74 1.98 1.98 ns lvcmos15_f4 0.77 0.86 0.93 0.96 1.85 1.97 2.23 2.23 1.87 2.00 2.24 2.24 ns lvcmos15_f8 0.77 0.86 0.93 0.96 1.60 1.72 1.98 1.98 1.62 1.75 1.99 1.99 ns lvcmos15_f12 0.77 0.86 0.93 0.96 1.35 1.47 1.73 1.73 1.37 1.50 1.74 1.74 ns lvcmos15_f16 0.77 0.86 0.93 0.96 1.34 1.46 1.71 2.07 1.35 1.49 1.73 2.09 ns lvcmos12_s4 0.87 0.95 1.02 1.19 2.57 2.69 2.95 2.95 2.59 2.72 2.96 2.96 ns lvcmos12_s8 0.87 0.95 1.02 1.19 2.09 2.21 2.46 2.46 2.10 2.24 2.48 2.48 ns lvcmos12_s12 0.87 0.95 1.02 1.19 1.79 1.91 2.17 2.17 1.81 1.94 2.18 2.18 ns lvcmos12_f4 0.87 0.95 1.02 1.19 1.98 2.10 2.35 2.35 1.99 2.13 2.37 2.37 ns lvcmos12_f8 0.87 0.95 1.02 1.19 1.54 1.66 1.92 1.92 1.56 1.69 1.93 1.93 ns lvcmos12_f12 0.87 0.95 1.02 1.19 1.38 1.51 1.76 1.76 1.40 1.54 1.77 1.77 ns sstl135_s 0.67 0.75 0.82 0.88 1.35 1. 47 1.73 1.73 1.37 1.50 1.74 1.74 ns sstl15_s 0.600.680.750.751.301.431.681.711.321.461.691.73 ns sstl18_i_s 0.670.750.820.861.671.792.042.041.681.822.062.06 ns sstl18_ii_s 0.67 0.75 0.82 0.88 1.31 1.43 1.68 1.68 1.32 1.46 1.70 1.70 ns diff_sstl135_s 0.68 0.76 0. 83 0.88 1.35 1.47 1.73 1. 73 1.37 1.50 1.74 1.74 ns diff_sstl15_s 0.68 0.76 0.83 0.88 1.30 1.43 1.68 1.71 1.32 1.46 1.69 1.73 ns diff_sstl18_i_s 0.71 0.79 0.86 0.88 1.68 1.80 2.06 2.06 1.70 1.83 2.07 2.07 ns diff_sstl18_ii_s 0.71 0.79 0.86 0.88 1.38 1.51 1.76 1. 76 1.40 1.54 1.77 1.77 ns sstl135_f 0.67 0.75 0.82 0.88 1.12 1. 24 1.49 1.49 1.13 1.27 1.51 1.51 ns sstl15_f 0.600.680.750.751.071.191.451.451.091.221.461.46 ns sstl18_i_f 0.670.750.820.861.121.241.491.531.131.271.511.54 ns sstl18_ii_f 0.67 0.75 0.82 0.88 1.12 1.24 1.49 1.51 1.13 1.27 1.51 1.52 ns diff_sstl135_f 0.68 0.76 0. 83 0.88 1.12 1.24 1.49 1. 49 1.13 1.27 1.51 1.51 ns diff_sstl15_f 0.68 0.76 0.83 0.88 1.07 1.19 1.45 1.45 1.09 1.22 1.46 1.46 ns diff_sstl18_i_f 0.71 0.79 0.86 0.88 1.23 1.35 1.60 1.60 1.24 1.38 1.62 1.62 ns diff_sstl18_ii_f 0.71 0.79 0.86 0.88 1.21 1.33 1.59 1. 59 1.23 1.36 1.60 1.60 ns table 52: iob high range (hr) switching characteristics (cont?d) i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade -3 -2 -1c/-1i/ -1li -1q -3 -2 -1c/-1i/ -1li -1q -3 -2 -1c/-1i/ -1li -1q s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 37 i/o standard adjustment measurement methodology input delay measurements table 54 shows the test setup parameters used for measuring input delay. table 53: iob 3-state output switching characteristics symbol description speed grade units -3 -2 -1c/-1i/-1li -1q t iotphz t input to pad high-impedance 2.06 2.19 2.37 2.37 ns t ioibufdisable ibuf turn-on time from ibufdisabl e to o output 2.11 2.30 2.60 2.60 ns table 54: input delay measurement methodology description i /o standard attribute v l (1)(2) v h (1)(2) v meas (1)(4)(6) v ref (1)(3)(5) lvcmos, 1.2v lvcmos12 0.1 1.1 0.6 ? lvcmos, 1.5v lvcmos15 0.1 1.4 0.75 ? lvcmos, 1.8v lvcmos18 0.1 1.7 0.9 ? lvcmos, 2.5v lvcmos25 0.1 2.4 1.25 ? lvcmos, 3.3v lvcmos33 0.1 3.2 1.65 ? lvttl, 3.3v lvttl 0.1 3.2 1.65 ? mobile_ddr, 1.8v mobile_ddr 0.1 1.7 0.9 ? pci33, 3.3v pci33_3 0.1 3.2 1.65 ? hstl (high-speed transceiver logic), class i, 1.2v hstl_i_12 v ref ?0.5 v ref +0.5 v ref 0.60 hstl, class i & ii, 1.5v hstl_i, hstl_ii v ref ?0.65 v ref +0.65 v ref 0.75 hstl, class i & ii, 1.8v hstl_i_18, hstl_ii_18 v ref ?0.8 v ref +0.8 v ref 0.90 hsul (high-speed unterminated logic), 1.2v hsul_12 v ref ?0.5 v ref +0.5 v ref 0.60 sstl (stub terminated transceiver logic), 1.2v sstl12 v ref ?0.5 v ref +0.5 v ref 0.60 sstl, 1.35v sstl135, sstl135_r v ref ? 0.575 v ref + 0.575 v ref 0.675 sstl, 1.5v sstl15, sstl15_r v ref ?0.65 v ref +0.65 v ref 0.75 sstl, class i & ii, 1.8v sstl18_i, sstl18_ii v ref ?0.8 v ref +0.8 v ref 0.90 diff_mobile_ddr, 1.8v diff_mo bile_ddr 0.9 ? 0.125 0.9 + 0.125 0 (6) ? diff_hstl, class i, 1.2v di ff_hstl_i_12 0.6 ? 0.125 0.6 + 0.125 0 (6) ? diff_hstl, class i & ii,1.5v diff_hstl_i, diff_hstl_ii 0.75 ? 0.125 0.75 + 0.125 0 (6) ? diff_hstl, class i & ii, 1.8v diff_hstl_i_18, diff_hstl_ii_18 0.9 ? 0.125 0.9 + 0.125 0 (6) ? diff_hsul, 1.2v diff_hsul _12 0.6 ? 0.125 0.6 + 0.125 0 (6) ? diff_sstl, 1.2v diff_sst l12 0.6 ? 0.125 0.6 + 0.125 0 (6) ? diff_sstl135/dif f_sstl135_r, 1.35v diff_sstl135, diff_sstl135_r 0.675 ? 0.125 0.675 + 0.125 0 (6) ? diff_sstl15/diff _sstl15_r, 1.5v diff_sstl15, diff_sstl15_r 0.75 ? 0.125 0.75 + 0.125 0 (6) ? diff_sstl18_i/di ff_sstl18_ii, 1.8v diff_sstl18_i, diff_sstl18_ii 0.9 ? 0.125 0.9 + 0.125 0 (6) ? lvds (low-voltage differential si gnaling), 1.8v lvds 0. 9 ? 0.125 0.9 + 0.125 0 (6) ? s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 38 output delay measurements output delays are measured with short ou tput traces. standard termination was used for all testing. the propagation delay of the trace is characterized separately and subtracted from the final measurement, and is therefore not included in the generalized test setups shown in figure 18 and figure 19 . lvds_25, 2.5v lvds_2 5 1.2 ? 0.125 1.2 + 0.125 0 (6) ? blvds_25, 2.5v blvds_25 1.25 ? 0.125 1.25 + 0.125 0 (6) ? mini_lvds_25, 2.5v mini_lvds _25 1.25 ? 0.125 1.25 + 0.125 0 (6) ? ppds_25 ppds_25 1.25 ? 0.125 1.25 + 0.125 0 (6) ? rsds_25 rsds_25 1.25 ? 0.125 1.25 + 0.125 0 (6) ? tmds_33 tmds_33 3 ? 0.125 3 + 0.125 0 (6) ? notes: 1. the input delay measurement methodology parameters for lvdci are the same for lvcmos standards of the same voltage. input del ay measurement methodology parameters for hslvdci are the same as fo r hstl_ii standards of the same voltage. parameters for all ot her dci standards are the same for the corresponding non-dci standards. 2. input waveform switches between v l and v h . 3. measurements are made at typical, minimum, and maximum v ref values. reported delays reflect worst case of these measurements. v ref values listed are typical. 4. input voltage level from which measurement starts. 5. this is an input voltage reference that bears no relation to the v ref / v meas parameters found in ibis models and/or noted in figure 18 . 6. the value given is the differential input voltage. x-ref target - figure 18 figure 18: single-ended test setup x-ref target - figure 19 figure 19: differential test setup table 54: input delay measurement methodology (cont?d) description i /o standard attribute v l (1)(2) v h (1)(2) v meas (1)(4)(6) v ref (1)(3)(5) v ref r ref v mea s (volt a ge level when t a king del a y me asu rement) c ref (pro b e c a p a cit a nce) fpga o u tp u t d s 1 8 7_20_090914 r ref v mea s + ? c ref fpga o u tp u t d s 1 8 7_21_090914 s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 39 parameters v ref , r ref , c ref , and v meas fully describe the test conditions for each i/o standard. the most accurate prediction of propagation delay in any given application can be obtained through ibis simulation, using this method: 1. simulate the output driver of choice into the generalized test setup using values from table 55 . 2. record the time to v meas . 3. simulate the output driver of choice into the actual pcb trace and load using the appropriate ibis model or capacitance value to represent the load. 4. record the time to v meas . 5. compare the results of step 2 and step 4 . the increase or decrease in delay yiel ds the actual propagation delay of the pcb trace. table 55: output delay measurement methodology description i/o standard attribute r ref ( ) c ref (1) (pf) v meas (v) v ref (v) lvcmos, 1.2v lvcmos12 1m 0 0.6 0 lvcmos/lvdci/hslvdci, 1.5v lvcmos 15, lvdci_15, hslvdci_15 1m 0 0.75 0 lvcmos/lvdci/hslvdci, 1.8v lvcmos 18, lvdci_15, hslvdci_18 1m 0 0.9 0 lvcmos, 2.5v lvcmos25 1m 0 1.25 0 lvcmos, 3.3v lvcmos33 1m 0 1.65 0 lvttl, 3.3v lvttl 1m 0 1.65 0 pci33, 3.3v pci33_3 25 10 1.65 0 hstl (high-speed transceiver logic), class i, 1.2v hstl_i_12 50 0 v ref 0.6 hstl, class i, 1.5v hstl_i 50 0 v ref 0.75 hstl, class ii, 1.5v hstl_ii 25 0 v ref 0.75 hstl, class i, 1.8v hstl_i_18 50 0 v ref 0.9 hstl, class ii, 1.8v hstl_ii_18 25 0 v ref 0.9 hsul (high-speed unterminated logic), 1.2v hsul_12 50 0 v ref 0.6 sstl12, 1.2v sstl12 50 0 v ref 0.6 sstl135/sstl135_r, 1.35v sstl135, sstl135_r 50 0 v ref 0.675 sstl15/sstl15_r, 1.5v sstl15, sstl15_r 50 0 v ref 0.75 sstl (stub series terminated logic), class i & class ii, 1.8v sstl18_i, sstl18_ii 50 0 v ref 0.9 diff_mobile_ddr, 1.8v diff_mobile_ddr 50 0 v ref 0.9 diff_hstl, class i, 1.2v diff_hstl_i_12 50 0 v ref 0.6 diff_hstl, class i & ii, 1.5v diff_hstl_i, diff_hstl_ii 50 0 v ref 0.75 diff_hstl, class i & ii, 1.8v diff _hstl_i_18, diff_hstl_ii_18 50 0 v ref 0.9 diff_hsul_12, 1.2v diff_hsul_12 50 0 v ref 0.6 diff_sstl12, 1.2v diff_sstl12 50 0 v ref 0.6 diff_sstl135/diff_sst l135_r, 1.35v diff_sstl135, diff_sstl135_r 50 0 v ref 0.675 diff_sstl15/diff_ sstl15_r, 1.5v diff_sstl1 5, diff_sstl15_r 50 0 v ref 0.75 diff_sstl18, class i & ii, 1.8v di ff_sstl18_i, diff_sstl18_ii 50 0 v ref 0.9 lvds (low-voltage differenti al signaling), 1.8v lvds 100 0 0 (2) 0 lvds, 2.5v lvds_25 100 0 0 (2) 0 blvds (bus lvds), 2.5v blvds_25 100 0 0 (2) 0 mini lvds, 2.5v mini_lvds_25 100 0 0 (2) 0 ppds_25 ppds_25 100 0 0 (2) 0 s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 40 input/output logic switching characteristics rsds_25 rsds_25 100 0 0 (2) 0 tmds_33 tmds_33 50 0 0 (2) 3.3 notes: 1. c ref is the capacitance of the probe, nominally 0 pf. 2. the value given is the differential output voltage. table 56: ilogic switching characteristics symbol description speed grade units -3 -2 -1c/-1i/-1li -1q setup/hold t ice1ck / t ickce1 ce1 pin setup/hold with respect to clk 0.48/0.02 0.54/0.02 0.76/0.02 0.76/0.02 ns t isrck / t icksr sr pin setup/hold with respect to clk 0.60/0.01 0.70/0.01 1.13/0.01 1.13/0.01 ns t idock / t iockd d pin setup/hold with respect to clk without delay 0.01/0.27 0.01/0.29 0.01/0.33 0.01/0.33 ns t idockd / t iockdd ddly pin setup/hold with respect to clk (using idelay) 0.02/0.27 0.02/0.29 0.02/0.33 0.02/0.33 ns combinatorial t idi d pin to o pin propagation delay, no delay 0.11 0.11 0.13 0.13 ns t idid ddly pin to o pin propagation delay (using idelay) 0.11 0.12 0.14 0.14 ns sequential delays t idlo d pin to q1 pin using flip-flop as a latch without delay 0.41 0.44 0.51 0.51 ns t idlod ddly pin to q1 pin using flip-flop as a latch (using idelay) 0.41 0.44 0.51 0.51 ns t ickq clk to q outputs 0.53 0.57 0.66 0.66 ns t rq_ilogic sr pin to oq/tq out 0.96 1.08 1.32 1.32 ns t gsrq_ilogic global set/reset to q outputs 7.60 7.60 10.51 10.51 ns set/reset t rpw_ilogic minimum pulse width, sr input s 0.61 0.72 0.72 0.72 ns, min table 57: ologic switching characteristics symbol description speed grade units -3 -2 -1c/-1i/-1li -1q setup/hold t odck / t ockd d1/d2 pins setup/hold with respect to cl k 0.67/?0.11 0.71/?0.11 0. 84/?0.11 0.84/?0.06 ns t ooceck / t ockoce oce pin setup/hold with respect to clk 0 .32/0.58 0.34/0.58 0.51/0.58 0.51/0.58 ns t osrck / t ocksr sr pin setup/hold with respect to clk 0.37/0.21 0.44/0.21 0.80/0.21 0.80/0.21 ns t otck / t ockt t1/t2 pins setup/hold with respect to clk 0.69/?0.14 0.73/?0.14 0. 89/?0.14 0.89/?0.11 ns table 55: output delay measurement methodology (cont?d) description i/o standard attribute r ref ( ) c ref (1) (pf) v meas (v) v ref (v) s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 41 input serializer/deserializer switching characteristics t otceck / t ocktce tce pin setup/hold with respect to clk 0 .32/0.01 0.34/0.01 0.51/0.01 0.51/0.01 ns combinatorial t odq d1 to oq out or t1 to tq out 0.83 0.96 1.16 1.16 ns sequential delays t ockq clk to oq/tq out 0.47 0.49 0.56 0.56 ns t rq_ologic sr pin to oq/tq ou t 0.72 0.80 0.95 0.95 ns t gsrq_ologic global set/reset to q outputs 7.60 7.60 10.51 10.51 ns set/reset t rpw_ologic minimum pulse width, sr inputs 0.64 0.74 0.74 0.74 ns, min table 58: iserdes switching characteristics symbol description speed grade units -3 -2 -1c/-1i/-1li -1q setup/hold for control lines t iscck_bitslip / t isckc_bitslip bitslip pin setup/hold with respect to cl kdiv 0.01/0.14 0.02/0.15 0.02/0.17 0.02/0.17 ns t iscck_ce / t isckc_ce (2) ce pin setup/hold with respect to clk (for ce1) 0.45/?0.01 0.50/?0.0 1 0.72/?0.01 0.72/?0.01 ns t iscck_ce2 / t isckc_ce2 (2) ce pin setup/hold with respect to clkdiv (for ce2) ?0.10/0.33 ?0.10/0.36 ? 0.10/0.40 ?0.10/0.40 ns setup/hold for data lines t isdck_d /t isckd_d d pin setup/hold with respect to clk ? 0.02/0.12 ?0.02/0.14 ?0. 02/0.17 ?0.02/0.17 ns t isdck_ddly / t isckd_ddly ddly pin setup/hold with respect to clk (using idelay) (1) ?0.02/0.12 ?0.02/0.14 ? 0.02/0.17 ?0.02/0.17 ns t isdck_d_ddr / t isckd_d_ddr d pin setup/hold with respect to clk at ddr mode ?0.02/0.12 ?0.02/0.14 ? 0.02/0.17 ?0.02/0.17 ns t isdck_ddly_ddr / t isckd_ddly_ddr d pin setup/hold with respect to clk at ddr mode (using idelay) (1) 0.12/0.12 0.14/0.14 0. 17/0.17 0.17/0.17 ns sequential delays t iscko_q clkdiv to out at q pin 0.53 0.54 0.66 0.66 ns propagation delays t isdo_do d input to do output pin 0.11 0.11 0.13 0.13 ns notes: 1. recorded at 0 tap value. 2. t iscck_ce2 and t isckc_ce2 are reported as t iscck_ce /t isckc_ce in the timing report. table 57: ologic switching characteristics (cont?d) symbol description speed grade units -3 -2 -1c/-1i/-1li -1q s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 42 output serializer/deserializer switching characteristics input/output delay switching characteristics table 59: oserdes switching characteristics symbol description speed grade units -3 -2 -1c/-1i/-1li -1q setup/hold t osdck_d / t osckd_d d input setup/hold with respect to clkdiv 0.42/0.03 0.45/0.03 0. 63/0.03 0.63/0.08 ns t osdck_t / t osckd_t (1) t input setup/hold with respect to clk 0.69/?0.13 0.73/?0.13 0. 88/?0.13 0.88/?0.13 ns t osdck_t2 / t osckd_t2 (1) t input setup/hold with respect to clkdiv 0.31/?0.13 0.34/?0.13 0. 39/?0.13 0.39/?0.13 ns t oscck_oce / t osckc_oce oce input setup/hold with respect to clk 0.32/0.58 0.34/0.58 0. 51/0.58 0.51/0.58 ns t oscck_s sr (reset) input setup with respect to clkdiv 0.47 0.52 0.85 0.85 ns t oscck_tce / t osckc_tce tce input setup/hold with respect to clk 0.32/0.01 0.34/0.01 0. 51/0.01 0.51/0.10 ns sequential delays t oscko_oq clock to out from clk to oq 0.40 0.42 0.48 0.48 ns t oscko_tq clock to out from clk to tq 0.47 0.49 0.56 0.56 ns combinatorial t osdo_ttq t input to tq out 0.83 0.92 1.11 1.11 ns notes: 1. t osdck_t2 and t osckd_t2 are reported as t osdck_t /t osckd_t in the timing report. table 60: input delay switching characteristics symbol description speed grade units -3 -2 -1c/-1i/-1li -1q idelayctrl t dlycco_rdy reset to ready for idel ayctrl 3.67 3.67 3.67 3.67 s f idelayctrl_ref attribute refclk frequency = 200.0 (1) 200 200 200 200 mhz attribute refclk frequency = 300.0 (1) 300 300 n/a n/a mhz attribute refclk frequency = 400.0 (1) 400 400 n/a n/a mhz idelayctrl_ ref_precision refclk precision 10 10 10 10 mhz t idelayctrl_rpw minimum reset pulse width 59.28 59.28 59.28 59.28 ns idelay t idelayresolution idelay chain delay resolution 1/(32 x 2 x f ref )ps s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 43 t idelaypat_jit and t odelaypat_jit pattern dependent period jitter in delay chain for clock pattern. (2) 0 0 0 0 ps per tap pattern dependent period jitter in delay chain for random data pattern (prbs 23) (3) refclk 200 mhz 5 5 5 5 ps per tap refclk 300 mhz 3.33 3.33 3.33 n/a ps per tap refclk 400 mhz 2.50 2.50 n/a n/a ps per tap pattern dependent period jitter in delay chain for random data pattern (prbs 23) (4) refclk 200 mhz 9.0 9.0 9.0 9.0 ps per tap refclk 300 mhz 6.0 6.0 6.0 n/a ps per tap refclk 400 mhz 4.5 4.5 n/a n/a ps per tap t idelay_clk_max maximum frequency of clk input to idelay 680.00 680.00 600.00 600.00 mhz t idcck_ce / t idckc_ce ce pin setup/hold with respect to c for id elay 0.12/0.11 0.16/0.13 0.21/0.16 0.21/0.16 ns t idcck_inc / t idckc_inc inc pin setup/hold with respect to c for id elay 0.12/0.16 0.14/0.18 0.16/0.22 0.16/0.23 ns t idcck_rst / t idckc_rst rst pin setup/hold with respect to c for idelay 0.15/0.09 0.16/0.11 0.18/0.14 0.18/0.14 ns t iddo_idatain propagation delay through idelay note 5 note 5 note 5 note 5 ps notes: 1. average tap delay at 200 mhz = 78 ps, at 300 mhz = 52 ps, and at 400 mhz = 39 ps. 2. when high_performance mode is set to true or false. 3. when high_performance mode is set to true. 4. when high_performance mode is set to false. 5. delay depends on idelay tap setting. see the timing report for actual values. table 61: io_fifo switching characteristics symbol description speed grade units -3 -2 -1c/-1i/-1li -1q io_fifo clock to out delays t offcko_do rdclk to q outputs 0.55 0.60 0.68 0.68 ns t cko_flags clock to io_fifo flags 0.55 0.61 0.77 0.77 ns setup/hold t cck_d /t ckc_d d inputs to wrclk 0.47/0.02 0. 51/0.02 0.58/0.02 0.58/0.18 ns t iffcck_wren / t iffckc_wren wren to wrclk 0.42/?0.01 0. 47/?0.01 0.53/?0.0 1 0.53/?0.01 ns t offcck_rden / t offckc_rden rden to rdclk 0.53/0.02 0.58/ 0.02 0.66/0.02 0.66/0.02 ns minimum pulse width t pwh_io_fifo reset, rdclk, wrclk 1.62 2.15 2.15 2.15 ns t pwl_io_fifo reset, rdclk, wrclk 1.62 2.15 2.15 2.15 ns maximum frequency f max rdclk and wrclk 266.67 200.00 200.00 200.00 mhz table 60: input delay switching characteristics (cont?d) symbol description speed grade units -3 -2 -1c/-1i/-1li -1q s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 44 clb switching characteristics clb distributed ram switching characteristics (slicem only) table 62: clb switching ch aracteristics symbol description speed grade units -3 -2 -1c/-1i/-1li -1q combinatorial delays t ilo an ? dn lut address to a 0.10 0.11 0.13 0.13 ns, max t ilo_2 an ? dn lut address to amux/cmux 0.27 0.30 0.36 0.36 ns, max t ilo_3 an ? dn lut address to bmux _a 0.42 0.46 0.55 0.55 ns, max t ito an ? dn inputs to a ? d q outpu ts 0.94 1.05 1.27 1.27 ns, max t axa ax inputs to amux output 0.62 0.69 0.84 0.84 ns, max t axb ax inputs to bmux output 0.58 0.66 0.83 0.83 ns, max t axc ax inputs to cmux output 0.60 0.68 0.82 0.82 ns, max t axd ax inputs to dmux output 0.68 0.75 0.90 0.90 ns, max t bxb bx inputs to bmux output 0.51 0.57 0.69 0.69 ns, max t bxd bx inputs to dmux output 0.62 0.69 0.82 0.82 ns, max t cxc cx inputs to cmux output 0.42 0.48 0.58 0.58 ns, max t cxd cx inputs to dmux output 0.53 0.59 0.71 0.71 ns, max t dxd dx inputs to dmux output 0.52 0.58 0.70 0.70 ns, max sequential delays t cko clock to aq ? dq outputs 0.40 0.44 0.53 0.53 ns, max t shcko clock to amux ? dmux outputs 0.47 0.53 0.66 0.66 ns, max setup and hold times of clb fl ip-flops before/after clock clk t as /t ah a n ? d n input to clk on a ? d flip-flops 0.07/0.12 0.09/0.14 0.11/0.18 0.11/0.28 ns, min t dick /t ckdi a x ?d x input to clk on a ? d flip-flops 0.06/0.19 0.07/0.21 0.09/0.26 0.09/0.35 ns, min a x ?d x input through muxs and/or carry logic to clk on a ? d flip-flops 0.59/0.08 0.66/0.09 0.81/0.11 0.81/0.20 ns, min t ceck_clb / t ckce_clb ce input to clk on a ? d flip-flops 0.15/0.00 0.17/0.00 0.21/0.01 0.21/0.13 ns, min t srck /t cksr sr input to clk on a ? d flip-flops 0.38/0.03 0.43/0.04 0.53/0.05 0.53/0.18 ns, min set/reset t srmin sr input minimum pulse width 0.52 0.78 1.04 1.04 ns, min t rq delay from sr input to aq ? dq fl ip-flops 0.53 0.59 0.71 0.71 ns, max t ceo delay from ce input to aq ? dq fl ip-flops 0.52 0.58 0.70 0.70 ns, max f tog toggle frequency (for export control) 1412 1286 1098 1098 mhz table 63: clb distributed ram swit ching characteristics symbol description speed grade units -3 -2 -1c/-1i/-1li -1q sequential delays t shcko (1) clock to a ? b outputs 0.98 1.09 1.32 1.32 ns, max t shcko_1 clock to amux ? bmux outputs 1.37 1.53 1.86 1.86 ns, max s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 45 clb shift register switching characteristics (slicem only) setup and hold times before/after clock clk t ds_lram / t dh_lram a ? d inputs to clk 0.54/0.28 0.60/0.30 0.72/0.35 0.72/0.37 ns, min t as_lram / t ah_lram address an inputs to clock 0.27/0.55 0.30/0.60 0.37/0.70 0.37/0.71 ns, min address an inputs through muxs and/or carry logic to clock 0.69/0.18 0.77/0.21 0.94/0.26 0.94/0.35 ns, min t ws_lram / t wh_lram we input to clock 0.38/0.10 0.43/0.12 0.53/0.17 0.53/0.17 ns, min t ceck_lram / t ckce_lram ce input to clk 0.39/0.10 0.44/0.11 0.53/0.17 0.53/0.17 ns, min clock clk t mpw_lram minimum pulse width 1.05 1.13 1.25 1.25 ns, min t mcp minimum clock period 2.10 2.26 2.50 2.50 ns, min notes: 1. t shcko also represents the clk to xmux output. refer to the timing report for the clk to xmux path. table 64: clb shift register switching characteristics symbol description speed grade units -3 -2 -1c/-1i/-1li -1q sequential delays t reg clock to a ? d outputs 1.19 1.33 1.61 1.61 ns, max t reg_mux clock to amux ? dmux output 1.58 1.77 2.15 2.15 ns, max t reg_m31 clock to dmux output via m31 output 1.12 1.23 1.46 1.46 ns, max setup and hold times before/after clock clk t ws_shfreg / t wh_shfreg we input 0.37/0.10 0.41/0.12 0.51/0.17 0.51/ 0.17 ns, min t ceck_shfreg / t ckce_shfreg ce input to clk 0.37/0.10 0.42 /0.11 0.52/0.17 0. 52/0.17 ns, min t ds_shfreg / t dh_shfreg a ? d inputs to clk 0.33/0.34 0.37 /0.37 0.44/0.43 0. 44/0.44 ns, min clock clk t mpw_shfreg minimum pulse width 0.77 0.86 0.98 0.98 ns, min table 63: clb distributed ram swit ching characteristics (cont?d) symbol description speed grade units -3 -2 -1c/-1i/-1li -1q s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 46 block ram and fifo switching characteristics table 65: block ram and fifo switching characteristics symbol description speed grade units -3 -2 -1c/-1i/-1li -1q block ram and fifo clock to out delays t rcko_do and t rcko_do_reg (1) clock clk to dout outp ut (without output register) (2)(3) 1.85 2.13 2.46 2.46 ns, max clock clk to dout output (with output register) (4)(5) 0.64 0.74 0.89 0.89 ns, max t rcko_do_ecc and t rcko_do_ecc_reg clock clk to dout output with ecc (without output register) (2)(3) 2.77 3.04 3.84 3.84 ns, max clock clk to dout ou tput with ecc (with output register) (4)(5) 0.73 0.81 0.94 0.94 ns, max t rcko_do_cascout and t rcko_do_cascout_reg clock clk to dout output with cascade (without output register) (2) 2.61 2.88 3.30 3.30 ns, max clock clk to dout output with cascade (with output register) (4) 1.16 1.28 1.46 1.46 ns, max t rcko_flags clock clk to fifo flags outputs (6) 0.76 0.87 1.05 1.05 ns, max t rcko_pointers clock clk to fifo pointers outputs (7) 0.94 1.02 1.15 1.15 ns, max t rcko_parity_ecc clock clk to eccparit y in ecc encode only mode 0.78 0.85 0.94 0.94 ns, max t rcko_sdbit_ecc and t rcko_sdbit_ecc_reg clock clk to biterr (without output register) 2.56 2.81 3.55 3.55 ns, max clock clk to biterr (with output register) 0.68 0.76 0.89 0.89 ns, max t rcko_rdaddr_ecc and t rcko_rdaddr_ecc_reg clock clk to rdaddr output with ecc (without output register) 0.75 0.88 1.07 1.07 ns, max clock clk to rdaddr output with ecc (with output register) 0.84 0.93 1.08 1.08 ns, max setup and hold times before/after clock clk t rcck_addra / t rckc_addra addr inputs (8) 0.45/0.31 0.49/0.33 0.57/0.36 0.57/0.52 ns, min t rdck_di_wf_nc / t rckd_di_wf_nc data input setup/hold time when block ram is configured in write_first or no_change mode (9) 0.58/0.60 0.65/0.63 0.74/0.67 0.74/0.67 ns, min t rdck_di_rf / t rckd_di_rf data input setup/hold time when block ram is configured in read_first mode (9) 0.20/0.29 0.22/0.34 0.25/0.41 0.25/0.50 ns, min t rdck_di_ecc / t rckd_di_ecc din inputs with block ram ecc in standard mode (9) 0.50/0.43 0.55/0.46 0.63/0.50 0.63/0.50 ns, min din inputs with block ram ecc encode only (9) 0.93/0.43 1.02/0.46 1.17/0.50 1.17/0.50 ns, min din inputs with fifo ecc in standard mode (9) 1.04/0.56 1.15/0.59 1.32/0.64 1.32/0.64 ns, min t rdck_di_eccw / t rckd_di_eccw din inputs with block ram ecc encode only (9) 0.93/0.43 1.02/0.46 1.17/0.50 1.17/0.50 ns, min t rdck_di_ecc_fifo / t rckd_di_ecc_fifo din inputs with fifo ecc in standard mode (9) 1.04/0.56 1.15/0.59 1.32/0.64 1.32/0.64 ns, min t rcck_injectbiterr / t rckc_injectbiterr inject single/double bit error in ecc mode 0.58/0.35 0.64/0.37 0.74/0.40 0.74/0.52 ns, min s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 47 t rcck_en / t rckc_en block ram enable (en) input 0.35/0.20 0.39/0.21 0.45/0.23 0.45/0.41 ns, min t rcck_regce / t rckc_regce ce input of output register 0.24/0.1 5 0.29/0.15 0.36/0.16 0.36/0.39 ns, min t rcck_rstreg / t rckc_rstreg synchronous rstreg input 0.29/0.07 0 .32/0.07 0.35/0.07 0.35/0.17 ns, min t rcck_rstram / t rckc_rstram synchronous rstram input 0.32/0.42 0. 34/0.43 0.36/0.46 0.36/0.57 ns, min t rcck_wea / t rckc_wea write enable (we) input (block ram only) 0.44 /0.18 0.48/0.19 0.54/0.20 0.54/0.42 ns, min t rcck_wren / t rckc_wren wren fifo inputs 0.46/0.30 0.46/ 0.35 0.47/0.43 0.47/0.43 ns, min t rcck_rden / t rckc_rden rden fifo inputs 0.42/ 0.30 0.43/0.35 0.43/0.43 0.43/0.62 ns, min reset delays t rco_flags reset rst to fifo flags/pointers (10) 0.90 0.98 1.10 1.10 ns, max t rrec_rst / t rrem_rst fifo reset recovery and removal timing (11) 1.87/?0.81 2.07/?0.81 2.37/ ?0.81 2.37/?0.58 ns, max maximum frequency f max_bram_wf_nc block ram (write first and no change modes) when not in sdp rf mode. 509.68 460.83 388.20 388.20 mhz f max_bram_rf_performa nce block ram (read first, performance mode) when in sdp rf mode but no address overlap between port a and port b. 509.68 460.83 388.20 388.20 mhz f max_bram_rf_delayed_ write block ram (read first, delayed write mode) when in sdp rf mode and there is possibility of overlap between port a and port b addresses. 447.63 404.53 339.67 339.67 mhz f max_cas_wf_nc block ram cascade (write first, no change mode) when cascade but not in rf mode. 467.07 418.59 345.78 345.78 mhz f max_cas_rf_performan ce block ram cascade (read first, performance mode) when in cascade with rf mode and no possibility of address overlap/one port is disabled. 467.07 418.59 345.78 345.78 mhz f max_cas_rf_delayed_w rite when in cascade rf mode and there is a possibility of address overlap between port a and port b. 405.35 362.19 297.35 297.35 mhz table 65: block ram and fifo switching characteristics (cont?d) symbol description speed grade units -3 -2 -1c/-1i/-1li -1q s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 48 f max_fifo fifo in all modes without ecc 509.68 460.83 388.20 388.20 mhz f max_ecc block ram and fifo in ecc conf iguration 410.34 365.10 297.53 297.53 mhz notes: 1. the timing report shows all of these parameters as t rcko_do . 2. t rcko_dor includes t rcko_dow , t rcko_dopr , and t rcko_dopw as well as the b port equivalent timing parameters. 3. these parameters also apply to synchronous fifo with do_reg = 0. 4. t rcko_do includes t rcko_dop as well as the b port equivalent timing parameters. 5. these parameters also apply to multirate (asynchronous) and synchronous fifo with do_reg = 1. 6. t rcko_flags includes the following parameters: t rcko_aempty , t rcko_afull , t rcko_empty , t rcko_full , t rcko_rderr , and t rcko_wrerr. 7. t rcko_pointers includes both t rcko_rdcount and t rcko_wrcount. 8. the addr setup and hold must be met when en is asserted (even when we is deasserted). otherwise, block ram data corruption is possible. 9. these parameters include both a and b inputs as well as the parity inputs of a and b. 10. t rco_flags includes the following flags: aempty, afull, empty, full, rderr, wrerr, rdcount, and wrcount. 11. rden and wren must be held low prior to and during reset. the fifo reset must be asserted for at least five positive clock e dges of the slowest clock (wrclk or rdclk). table 65: block ram and fifo switching characteristics (cont?d) symbol description speed grade units -3 -2 -1c/-1i/-1li -1q s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 49 dsp48e1 switching characteristics table 66: dsp48e1 switching characteristics symbol description speed grade units -3 -2 -1c/-1i/-1li -1q setup and hold times of data/control pins to the input register clock t dspdck_a_areg / t dspckd_a_areg a input to a register clk 0.26/0. 12 0.30/0.13 0.37/ 0.14 0.37/0.28 ns t dspdck_b_breg /t dspckd_b_breg b input to b register clk 0.33/0. 15 0.38/0.16 0.45/ 0.18 0.45/0.25 ns t dspdck_c_creg /t dspckd_c_creg c input to c register clk 0.17/0. 17 0.20/0.19 0.24/ 0.21 0.24/0.26 ns t dspdck_d_dreg /t dspckd_d_dreg d input to d register clk 0.25/0. 25 0.32/0.27 0.42/ 0.27 0.42/0.42 ns t dspdck_acin_areg / t dspckd_acin_areg acin input to a register clk 0.2 3/0.12 0.27/0.13 0. 32/0.14 0.32/0.17 ns t dspdck_bcin_breg / t dspckd_bcin_breg bcin input to b register clk 0.2 5/0.15 0.29/0.16 0. 36/0.18 0.36/0.18 ns setup and hold times of data pins to the pipeline register clock t dspdck_ { a, b } _mreg_mult / t dspckd_ { a, b}_mreg_mult { a, b} input to m register clk using multiplier 2.40/?0.01 2.76/?0.01 3. 29/?0.01 3.29/?0.01 ns t dspdck_ { a, d } _adreg / t dspckd_ { a, d}_adreg { a, d} input to ad register clk 1.2 9/?0.02 1.48/?0. 02 1.76/?0.02 1.76/?0.02 ns setup and hold times of data/control pins to the output register clock t dspdck_ { a, b}_preg_mult / t dspckd_ { a, b} _preg_mult { a, b} input to p register clk using multiplier 4.02/?0.28 4.60/?0.28 5. 48/?0.28 5.48/?0.28 ns t dspdck_d_preg_mult / t dspckd_d_preg_mult d input to p register clk using multiplier 3.93/?0.73 4.50/?0.73 5. 35/?0.73 5.35/?0.73 ns t dspdck_ { a, b} _preg / t dspckd_ { a, b} _preg a or b input to p register clk not using multiplier 1.73/?0.28 1.98/?0.28 2. 35/?0.28 2.35/?0.28 ns t dspdck_c_preg / t dspckd_c_preg c input to p register clk not using multiplier 1.54/?0.26 1.76/?0.26 2. 10/?0.26 2.10/?0.26 ns t dspdck_pcin_preg / t dspckd_pcin_preg pcin input to p register clk 1.32/ ?0.15 1.51/?0.15 1.80/?0.15 1.80/?0.15 ns setup and hold times of the ce pins t dspdck_ { cea;ceb}_ { areg;breg} / t dspckd_ { cea;ceb}_ { areg;breg} { cea; ceb} input to { a; b} register clk 0.35/0.06 0.42/0.08 0.52/0.11 0.52/0.11 ns t dspdck_cec_creg / t dspckd_cec_creg cec input to c register clk 0.28/ 0.10 0.34/0.11 0. 42/0.13 0.42/0.13 ns t dspdck_ced_dreg / t dspckd_ced_dreg ced input to d register clk 0.36/?0. 03 0.43/?0.03 0.52/?0.03 0.52/?0.03 ns t dspdck_cem_mreg / t dspckd_cem_mreg cem input to m register clk 0.17/ 0.18 0.21/0.20 0. 27/0.23 0.27/0.23 ns t dspdck_cep_preg / t dspckd_cep_preg cep input to p register clk 0.36/ 0.01 0.43/0.01 0. 53/0.01 0.53/0.01 ns setup and hold times of the rst pins t dspdck_ { rsta; rstb}_ { areg; breg} / t dspckd_ { rsta; rstb}_ { areg; breg} { rsta, rstb} input to { a, b} register clk 0.41/0.11 0.46/0.13 0.55/0.15 0.55/0.24 ns t dspdck_rstc_creg / t dspckd_rstc_creg rstc input to c register clk 0.07/ 0.10 0.08/0.11 0. 09/0.12 0.09/0.25 ns t dspdck_rstd_dreg / t dspckd_rstd_dreg rstd input to d register clk 0.44/ 0.07 0.50/0.08 0. 59/0.09 0.59/0.09 ns t dspdck_rstm_mreg / t dspckd_rstm_mreg rstm input to m register clk 0.21/ 0.22 0.23/0.24 0. 27/0.28 0.27/0.28 ns s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 50 t dspdck_rstp_preg / t dspckd_rstp_preg rstp input to p register clk 0.27/ 0.01 0.30/0.01 0. 35/0.01 0.35/0.03 ns combinatorial delays from input pins to output pins t dspdo_a_carryout_mult a input to carryout output using multiplier 3.79 4.35 5.18 5.18 ns t dspdo_d_p_mult d input to p output using multiplier 3.72 4.26 5.07 5.07 ns t dspdo_a_p a input to p output not using multiplier 1.53 1.75 2.08 2.08 ns t dspdo_c_p c input to p output 1.33 1.53 1.82 1.82 ns combinatorial delays from input pins to cascading output pins t dspdo_ { a; b}_ { acout; bcout} { a, b} input to { acout, bcout} output 0.55 0.63 0.74 0.74 ns t dspdo_ { a, b}_carrycascout_mult { a, b} input to carrycascout output using multiplier 4.06 4.65 5.54 5.54 ns t dspdo_d_carr ycascout_mult d input to carrycascout output using multiplier 3.97 4.54 5.40 5.40 ns t dspdo_ { a, b}_carrycascout { a, b} input to carrycascout output not using multiplier 1.77 2.03 2.41 2.41 ns t dspdo_c_carrycascout c input to carrycascout output 1.58 1.81 2.15 2.15 ns combinatorial delays from cascading input pins to all output pins t dspdo_acin_p_mult acin input to p output using multiplier 3.65 4.19 5.00 5.00 ns t dspdo_acin_p acin input to p output not using multiplier 1.37 1.57 1.88 1.88 ns t dspdo_acin_acout acin input to acout output 0.38 0.44 0.53 0.53 ns t dspdo_acin_car rycascout_mult acin input to carrycascout output using multiplier 3.90 4.47 5.33 5.33 ns t dspdo_acin_carrycascout acin input to carrycascout output not using multiplier 1.61 1.85 2.21 2.21 ns t dspdo_pcin_p pcin input to p output 1.11 1.28 1.52 1.52 ns t dspdo_pcin_carrycascout pcin input to carrycascout output 1.36 1.56 1.85 1.85 ns clock to outs from output re gister clock to output pins t dspcko_p_preg clk preg to p output 0.33 0.37 0.44 0.44 ns t dspcko_carrycascout_preg clk preg to carrycascout output 0.52 0.59 0.69 0.69 ns clock to outs from pipeline register clock to output pins t dspcko_p_mreg clk mreg to p output 1.68 1.93 2.31 2.31 ns t dspcko_carrycascout_mreg clk mreg to carrycascout output 1.92 2.21 2.64 2.64 ns t dspcko_p_adreg_mult clk adreg to p output using multiplier 2.72 3.10 3.69 3.69 ns t dspcko_carrycascout_adreg_mult clk adreg to carrycascout output using multiplier 2.96 3.38 4.02 4.02 ns table 66: dsp48e1 switching characteristics (cont?d) symbol description speed grade units -3 -2 -1c/-1i/-1li -1q s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 51 clock to outs from input re gister clock to output pins t dspcko_p_areg_mult clk areg to p output using multiplier 3.94 4.51 5.37 5.37 ns t dspcko_p_breg clk breg to p output not using multiplier 1.64 1.87 2.22 2.22 ns t dspcko_p_creg clk creg to p output not using multiplier 1.69 1.93 2.30 2.30 ns t dspcko_p_dreg_mult clk dreg to p output using multiplier 3.91 4.48 5.32 5.32 ns clock to outs from input register clock to cascadi ng output pins t dspcko_ { acout; bcout}_ { areg; breg} clk (acout, bcout) to { a,b} register output 0.64 0.73 0.87 0.87 ns t dspcko_carrycascout_ { areg, breg}_mult clk (areg, breg) to carrycascout output using multiplier 4.19 4.79 5.70 5.70 ns t dspcko_carrycascout_breg clk breg to carrycascout output not using multiplier 1.88 2.15 2.55 2.55 ns t dspcko_carrycascout_dreg_mult clk dreg to carrycascout output using multiplier 4.16 4.76 5.65 5.65 ns t dspcko_carrycascout_creg clk creg to carrycascout output 1.94 2.21 2.63 2.63 ns maximum frequency f max with all registers used 628.93 550.66 464.25 464.25 mhz f max_patdet with pattern detector 531.63 465.77 392.93 392.93 mhz f max_mult_nomreg two register multiply without mreg 349.28 305.62 257.47 257.47 mhz f max_mult_nomreg_patdet two register multiply without mreg with pattern detect 317.26 277.62 233.92 233.92 mhz f max_preadd_mult_noadreg without adreg 397.30 346.26 290.44 290.44 mhz f max_preadd_mult_noadreg_patdet without adreg with pattern detect 397.30 346.26 290.44 290.44 mhz f max_nopipelinereg without pipeline registers (mreg, adreg) 260.01 227.01 190.69 190.69 mhz f max_nopipelinereg_patdet without pipeline registers (mreg, adreg) with pattern detect 241.72 211.15 177.43 177.43 mhz table 66: dsp48e1 switching characteristics (cont?d) symbol description speed grade units -3 -2 -1c/-1i/-1li -1q s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 52 clock buffers and networks table 67: global clock switching charac teristics (including bufgctrl) symbol description speed grade units -3 -2 -1c/-1i/-1li -1q t bccck_ce /t bcckc_ce (1) ce pins setup/hold 0.13/0.39 0. 14/0.41 0.18/0.42 0.18/0.84 ns t bccck_s /t bcckc_s (1) s pins setup/hold 0.13/0.39 0. 14/0.41 0.18/0.42 0.18/0.84 ns t bccko_o (2) bufgctrl delay from i0/i1 to o 0.08 0.09 0.11 0.11 ns maximum frequency f max_bufg global clock tree (bufg) 628.00 628.00 464.00 464.00 mhz notes: 1. t bccck_ce and t bcckc_ce must be satisfied to assure glitch-free operation of the global clock when switching between clocks. these parameters do not apply to the bufgmux primitive that assures glitch-free operation. the other global clock setup and hold time s are optional; only needing to be satisfied if device operation requires simulation matc hes on a cycle-for-cycle basis when switchin g between clocks. 2. t bgcko_o (bufg delay from i0 to o) values are the same as t bccko_o values. table 68: input/output clock switching characteristics (bufio) symbol description speed grade units -3 -2 -1c/-1i/-1li -1q t biocko_o clock to out delay from i to o 1.16 1.32 1.61 1.61 ns maximum frequency f max_bufio i/o clock tree (bufio) 680.00 680.00 600.00 600.00 mhz table 69: regional clock buffer swit ching characteristics (bufr) symbol description speed grade units -3 -2 -1c/-1i/-1li -1q t brcko_o clock to out delay from i to o 0.64 0.80 1.04 1.04 ns t brcko_o_byp clock to out delay from i to o with divide bypass attribute set 0.35 0.41 0.54 0.54 ns t brdo_o propagation delay from clr to o 0.85 0.89 1.14 1.14 ns maximum frequency f max_bufr (1) regional clock tree (bufr) 420.00 375.00 315.00 315.00 mhz notes: 1. the maximum input frequency to the bufr and bufmr is the bufio f max frequency. table 70: horizontal clock buffer swit ching characteristics (bufh) symbol description speed grade units -3 -2 -1c/-1i/-1li -1q t bhcko_o bufh delay from i to o 0.11 0.11 0.14 0.14 ns t bhcck_ce /t bhckc_ce ce pin setup and hold 0.20/0.13 0.23/0.16 0.29/0.21 0.29/0.43 ns maximum frequency f max_bufh horizontal clock buffer (b ufh) 628.00 628.00 464.00 464.00 mhz s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 53 mmcm switching characteristics table 71: duty-cycle distortion and clock-tree skew symbol description device speed grade units -3 -2 -1c/-1i/-1li -1q t dcd_clk global clock tree duty-cycle distortion (1) all 0.20 0.20 0.20 0.20 ns t ckskew global clock tree skew (2) xc7z007s n/a 0.27 0.27 n/a ns xc7z012s n/a 0.39 0.42 n/a ns xc7z014s n/a 0.38 0.42 n/a ns XC7Z010 0.27 0.27 0.27 n/a ns xc7z015 0.33 0.39 0.42 n/a ns xc7z020 0.33 0.38 0.42 n/a ns xa7z010 n/a n/a 0.27 0.27 ns xa7z020 n/a n/a 0.42 0.42 ns xq7z020 n/a 0.38 0.42 0.42 ns t dcd_bufio i/o clock tree duty-cycle dist ortion all 0.14 0.14 0.14 0.14 ns t bufioskew i/o clock tree skew across one cl ock region all 0.03 0.03 0.03 0.03 ns t dcd_bufr regional clock tree duty-cycle distortion all 0.18 0.18 0.18 0.18 ns notes: 1. these parameters represent the worst-case du ty-cycle distortion observable at the pins of the device using lvds output buffer s. for cases where other i/o standards are used, ibis can be used to calcul ate any additional duty-cycle distortion that might be caused by asymmetrical rise/fall times. 2. the t ckskew value represents the worst-case clock-tree skew observable between sequential i/o elements. significantly less clock-tree skew exists for i/o registers that are close to each other and fed by the same or adjacent clock-tree branches. use the xilinx timing analyzer tools to evaluate application specific clock skew. table 72: mmcm specification symbol description speed grade units -3 -2 -1c/-1i/-1li -1q mmcm_f inmax maximum input clock frequency 800.00 800.00 800.00 800.00 mhz mmcm_f inmin minimum input clock frequ ency 10.00 10.00 10.00 10.00 mhz mmcm_f injitter maximum input clock period jitter < 20% of clock input period or 1 ns max mmcm_f induty allowable input duty cycle: 10?49 mhz 25 25 25 25 % allowable input duty cycle: 50?199 mhz 30 30 30 30 % allowable input duty cycle: 200?399 mhz 35 35 35 35 % allowable input duty cycle: 400?499 mhz 40 40 40 40 % allowable input duty cycle: >500 mhz 45 45 45 45 % mmcm_f min_psclk minimum dynamic phase-shift clock frequency 0.01 0.01 0.01 0.01 mhz mmcm_f max_psclk maximum dynamic phase-shift clock frequency 550.00 500.00 450.00 450.00 mhz mmcm_f vcomin minimum mmcm vco frequency 600.00 600.00 600.00 600.00 mhz mmcm_f vcomax maximum mmcm vco frequency 1600.00 1440.00 1200.00 1200.00 mhz mmcm_f bandwidth low mmcm bandwidth at typical (1) 1.00 1.00 1.00 1.00 mhz high mmcm bandwidth at typical (1) 4.00 4.00 4.00 4.00 mhz mmcm_t statphaoffset static phase offset of the mmcm outputs (2) 0.12 0.12 0.12 0.12 ns mmcm_t outjitter mmcm output jitter note 3 mmcm_t outduty mmcm output clock duty-cycle precision (4) 0.20 0.20 0.20 0.20 ns s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 54 mmcm_t lockmax mmcm maximum lock time 100.00 100.00 100.00 100.00 s mmcm_f outmax mmcm maximum output frequency 800.00 800.00 800.00 800.00 mhz mmcm_f outmin mmcm minimum output frequency (5)(6) 4.69 4.69 4.69 4.69 mhz mmcm_t extfdvar external clock feedback variation < 20% of clock input period or 1 ns max mmcm_rst minpulse minimum reset pulse width 5.00 5.00 5.00 5.00 ns mmcm_f pfdmax maximum frequency at the phase frequency detector 550.00 500.00 450.00 450.00 mhz mmcm_f pfdmin minimum frequency at the phase frequency detector 10.00 10.00 10.00 10.00 mhz mmcm_t fbdelay maximum delay in the feedback path 3 ns max or one clkin cycle mmcm switching character istics setup and hold t mmcmdck_psen / t mmcmckd_psen setup and hold of phase-shift enable 1 .04/0.00 1.04/0.00 1. 04/0.00 1.04/0.00 ns t mmcmdck_psincdec / t mmcmckd_psincdec setup and hold of phase-shift increment/decrement 1.04/0.00 1.04/0.00 1. 04/0.00 1.04/0.00 ns t mmcmcko_psdone phase shift clock-to-out of psdone 0.59 0.68 0.81 0.81 ns dynamic reconfiguration port (drp ) for mmcm before and after dclk t mmcmdck_daddr / t mmcmckd_daddr daddr setup/hold 1.25/0.15 1.40/0. 15 1.63/0.15 1.63/0.15 ns, min t mmcmdck_di / t mmcmckd_di di setup/hold 1.25/0.15 1.40/0. 15 1.63/0.15 1.63/0.15 ns, min t mmcmdck_den / t mmcmckd_den den setup/hold 1.76/0. 00 1.97/0.00 2.29/0.00 2.29/0.00 ns, min t mmcmdck_dwe / t mmcmckd_dwe dwe setup/hold 1.25/0.15 1.40/0. 15 1.63/0.15 1.63/0.15 ns, min t mmcmcko_drdy clk to out of drdy 0.65 0.72 0.99 0.99 ns, max f dck dclk frequency 200.00 200.00 200.00 200.00 mhz, max notes: 1. the mmcm does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequen cies. 2. the static offset is measured between any mmcm outputs with identical phase. 3. values for this parameter are available in the clocking wizard. see http://www.xilinx.c om/products/intell ectual-property/cl ocking_wizard.htm . 4. includes global clock buffer. 5. calculated as f vco /128 assuming output duty cycle is 50%. 6. when clkout4_cascade = true, mmcm_f outmin is 0.036 mhz. table 72: mmcm specification (cont?d) symbol description speed grade units -3 -2 -1c/-1i/-1li -1q s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 55 pll switching characteristics table 73: pll specification symbol description speed grade units -3 -2 -1c/-1i/-1li -1q pll_f inmax maximum input clock frequency 800.00 800.00 800.00 800.00 mhz pll_f inmin minimum input clock frequency 19.00 19.00 19.00 19.00 mhz pll_f injitter maximum input clock period jitter < 20% of clock input period or 1 ns max pll_f induty allowable input duty cycle: 19?49 mhz 25 25 25 25 % allowable input duty cycl e: 50?199 mhz 30 30 30 30 % allowable input duty cycl e: 200?399 mhz 35 35 35 35 % allowable input duty cycl e: 400?499 mhz 40 40 40 40 % allowable input duty cycle: >500 mhz 45 45 45 45 % pll_f vcomin minimum pll vco frequency 800.00 800.00 800.00 800.00 mhz pll_f vcomax maximum pll vco frequency 213 3.00 1866.00 1600.00 1600.00 mhz pll_f bandwidth low pll bandwidth at typical (1) 1.00 1.00 1.00 1.00 mhz high pll bandwidth at typical (1) 4.00 4.00 4.00 4.00 mhz pll_t statphaoffset static phase offset of the pll outputs (2) 0.12 0.12 0.12 0.12 ns pll_t outjitter pll output jitter note 3 pll_t outduty pll output clock duty-cycle precision (4) 0.20 0.20 0.20 0.20 ns pll_t lockmax pll maximum lock time 100.00 100.00 100.00 100.00 s pll_f outmax pll maximum output frequenc y 800.00 800.00 800.00 800.00 mhz pll_f outmin pll minimum output frequency (5) 6.25 6.25 6.25 6.25 mhz pll_t extfdvar external clock feedback variation < 20% of clock input period or 1 ns max pll_rst minpulse minimum reset pulse width 5.00 5.00 5.00 5.00 ns pll_f pfdmax maximum frequency at the phase frequency detector 550.00 500.00 450.00 450.00 mhz pll_f pfdmin minimum frequency at the phase frequency detector 19.00 19.00 19.00 19.00 mhz pll_t fbdelay maximum delay in the feedback path 3 ns max or one clkin cycle dynamic reconfiguration port (drp ) for pll before and after dclk t pllcck_daddr /t pllckc _daddr setup and hold of d address 1.25/0.15 1.40/0.15 1.63/0.15 1.63/0.15 ns, min t pllcck_di /t pllckc_di setup and hold of d input 1.25/0.15 1 .40/0.15 1.63/0.15 1. 63/0.15 ns, min t pllcck_den /t pllckc_ den setup and hold of d enable 1.76/0.00 1.97/0.00 2.29/0.00 2.29/0.00 ns, min t pllcck_dwe /t pllckc_ dwe setup and hold of d write enable 1.25/0. 15 1.40/0.15 1.63/0.15 1.63/0.15 ns, min t pllcko_drdy clk to out of drdy 0.65 0.72 0.99 0.99 ns, max f dck dclk frequency 200.00 200.00 200.00 200.00 mhz, max notes: 1. the pll does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequenc ies. 2. the static offset is measured between any pll outputs with identical phase. 3. values for this parameter are available in the clocking wizard. see http://www.xilinx.c om/products/intell ectual-property/cl ocking_wizard.htm . 4. includes global clock buffer. 5. calculated as f vco /128 assuming output duty cycle is 50%. s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 56 device pin-to-pin output parameter guidelines table 74: clock-capable clock input to output de lay without mmcm/pll (near clock region) (1) symbol description device speed grade units -3 -2 -1c/-1i/-1li -1q sstl15 clock-capable clock input to output dela y using output flip-flops, fast slew rate, without mmcm/pll. t ickof clock-capable clock input and outff at pins/banks closest to the bufgs without mmcm/pll (near clock region) (2) xc7z007s n/a 5.68 6.65 n/a ns xc7z012s n/a 5.96 6.90 n/a ns xc7z014s n/a 6.05 7.08 n/a ns XC7Z010 5.08 5.68 6.65 n/a ns xc7z015 5.34 5.96 6.90 n/a ns xc7z020 5.42 6.05 7.08 n/a ns xa7z010 n/a n/a 6.65 6.65 ns xa7z020 n/a n/a 7.08 7.08 ns xq7z020 n/a 6.05 7.08 7.08 ns notes: 1. this table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. refer to the die level bank numbering overview section of zynq-7000 all programmable soc packaging and pinout specification ( ug 865 ). table 75: clock-capable clock input to output de lay without mmcm/pll (far clock region) (1) symbol description device speed grade units -3 -2 -1c/-1i/-1li -1q sstl15 clock-capable clock input to output dela y using output flip-flops, fast slew rate, without mmcm/pll. t ickoffar clock-capable clock input and outff at pins/banks farthest from the bufgs without mmcm/pll (far clock region) (2) xc7z007s n/a 5.68 6.65 n/a ns xc7z012s n/a 6.25 7.21 n/a ns xc7z014s n/a 6.34 7.40 n/a ns XC7Z010 5.08 5.68 6.65 n/a ns xc7z015 5.60 6.25 7.21 n/a ns xc7z020 5.69 6.34 7.40 n/a ns xa7z010 n/a n/a 6.65 6.65 ns xa7z020 n/a n/a 7.40 7.40 ns xq7z020 n/a 6.34 7.40 7.40 ns notes: 1. this table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. refer to the die level bank numbering overview section of zynq-7000 all programmable soc packaging and pinout specification ( ug865 ). s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 57 table 76: clock-capable clock input to output delay with mmcm symbol description device speed grade units -3 -2 -1c/-1i/-1li -1q sstl15 clock-capable clock input to output dela y using output flip-flops, fast slew rate, with mmcm. t ickofmmcmcc clock-capable clock input and outff with mmcm xc7z007s n/a 1.03 1.03 n/a ns xc7z012s n/a 1.04 1.06 n/a ns xc7z014s n/a 1.04 1.05 n/a ns XC7Z010 1.04 1.03 1.03 n/a ns xc7z015 1.05 1.04 1.06 n/a ns xc7z020 1.05 1.04 1.05 n/a ns xa7z010 n/a n/a 1.03 1.03 ns xa7z020 n/a n/a 1.05 1.05 ns xq7z020 n/a 1.04 1.05 1.05 ns notes: 1. this table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. mmcm output jitter is already included in the timing calculation. table 77: clock-capable clock input to output delay with pll symbol description device speed grade units -3 -2 -1c/-1i/-1li -1q sstl15 clock-capable clock input to output dela y using output flip-flops, fast slew rate, with pll. t ickofpllcc clock-capable clock input and outff with pll xc7z007s n/a 0.82 0.82 n/a ns xc7z012s n/a 0.82 0.82 n/a ns xc7z014s n/a 0.82 0.82 n/a ns XC7Z010 0.82 0.82 0.82 n/a ns xc7z015 0.82 0.82 0.82 n/a ns xc7z020 0.82 0.82 0.82 n/a ns xa7z010 n/a n/a 0.82 0.82 ns xa7z020 n/a n/a 0.82 0.82 ns xq7z020 n/a 0.82 0.82 0.82 ns notes: 1. this table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. pll output jitter is already included in the timing calculation. table 78: pin-to-pin, clock-to-out using bufio symbol description speed grade units -3 -2 -1c/-1i/-1li -1q sstl15 clock-capable clock input to output delay us ing output flip-flop, fast slew rate, with bufio. t ickofcs clock to out of i/o clock 5.14 5.76 6.81 6.81 ns s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 58 device pin-to-pin input parameter guidelines table 79: global clock input setup and hold without mmcm/pll with zhold_delay on hr i/o banks symbol description device speed grade units -3 -2 -1c/-1i/-1li -1q input setup and hold time relative to global clock input signal for sstl15 standard. (1) t psfd / t phfd full delay (legacy delay or default delay) global clock input and iff (2) without mmcm/pll with zhold_delay on hr i/o banks xc7z007s n/a 2.13/?0. 17 2.44/?0.17 n/a ns xc7z012s n/a 2.55/?0. 18 3.03/?0.18 n/a ns xc7z014s n/a 2.74/?0. 25 3.18/?0.25 n/a ns XC7Z010 2.00/?0.17 2.13 /?0.17 2.44/?0.17 n/a ns xc7z015 2.38/?0.18 2.55 /?0.18 3.03/?0.18 n/a ns xc7z020 2.55/?0.25 2.74 /?0.25 3.18/?0.25 n/a ns xa7z010 n/a n/a 2.44/ ?0.17 2.44/?0.17 ns xa7z020 n/a n/a 3.18/ ?0.25 3.18/?0.25 ns xq7z020 n/a 2.74/?0.25 3.18/?0.25 3.18/?0.25 ns notes: 1. setup and hold times are measured over worst case conditions (pro cess, voltage, temperature). setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage. 2. iff = input flip-flop or latch. table 80: clock-capable clock input setup and hold with mmcm symbol description device speed grade units -3 -2 -1c/-1i/-1li -1q input setup and hold time relative to global clock input signal for sstl15 standard. (1) t psmmcmcc / t phmmcmcc no delay clock-capable clock input and iff (2) with mmcm xc7z007s n/a 2.68/?0. 62 3.22/?0.62 n/a ns xc7z012s n/a 2.80/?0. 62 3.34/?0.62 n/a ns xc7z014s n/a 2.82/?0. 62 3.38/?0.62 n/a ns XC7Z010 2.36/?0.62 2.68/ ?0.62 3.22/?0.62 n/a ns xc7z015 2.47/?0.62 2.80/ ?0.62 3.34/?0.62 n/a ns xc7z020 2.48/?0.62 2.82/ ?0.62 3.38/?0.62 n/a ns xa7z010 n/a n/a 3.22/?0.62 3.22/?0.62 ns xa7z020 n/a n/a 3.38/?0.62 3.38/?0.62 ns xq7z020 n/a 2.82/?0.62 3. 38/?0.62 3.38/?0.62 ns notes: 1. setup and hold times are measured over worst case conditions (p rocess, voltage, temperature). setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. hold time is measured relative to the gl obal clock input signal using the fastest process, lowest temperature, and highest voltage. 2. iff = input flip-flop or latch 3. use ibis to determine any duty-cycle distortion incurred using various standards. s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 59 table 81: clock-capable clock input setup and hold with pll symbol description device speed grade units -3 -2 -1c/-1i/-1li -1q input setup and hold time relative to clock-capable clock input signal for sstl15 standard. (1) t pspllcc / t phpllcc no delay clock-capable clock input and iff (2) with pll xc7z007s n/a 3.03/?0.19 3.64/?0.19 n/a ns xc7z012s n/a 3.15/?0.20 3.76/?0.20 n/a ns xc7z014s n/a 3.17/?0.20 3.80/?0.20 n/a ns XC7Z010 2.67/?0.19 3.03/? 0.19 3.64/?0.19 n/a ns xc7z015 2.78/?0.20 3.15/? 0.20 3.76/?0.20 n/a ns xc7z020 2.79/?0.20 3.17/? 0.20 3.80/?0.20 n/a ns xa7z010 n/a n/a 3.6 4/?0.19 3.64/?0.19 ns xa7z020 n/a n/a 3.8 0/?0.20 3.80/?0.20 ns xq7z020 n/a 3.17/?0.20 3 .80/?0.20 3.80/?0.20 ns notes: 1. setup and hold times are measured over worst case conditions (process, voltage, temperature). setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. hold time is measured relative to the gl obal clock input signal using the fastest process, lowest temperature, and highest voltage. 2. iff = input flip-flop or latch 3. use ibis to determine any duty-cycle distortion incurred using various standards. table 82: data input setup and hold times relative to a forwarded clock input pin using bufio symbol description speed grade units -3 -2 -1c/-1i/-1li -1q input setup and hold time relative to a forwarded clock input pin using bufio for sstl15 standard. t pscs /t phcs setup and hold of i/o clock ?0.38/ 1.39 ?0.38/1.55 ?0.38/ 1.86 ?0.38/1.86 ns table 83: sample window symbol description speed grade units -3 -2 -1c/-1i/-1li -1q t samp sampling error at receiver pins (1) 0.59 0.64 0.70 0.70 ns t samp_bufio sampling error at receiver pins using bufio (2) 0.35 0.40 0.46 0.46 ns notes: 1. this parameter indicates the total sampling error of the pl ddr input registers, measured across voltage, temperature, and pr ocess. the characterization methodology uses the mmcm to capture the ddr i nput registers? edges of operation. these measurements include: - clk0 mmcm jitter - mmcm accuracy (phase offset) - mmcm phase shift resolution these measurements do not include package or clock tree skew. 2. this parameter indicates the total sampling error of the pl ddr input registers, measured across voltage, temperature, and pr ocess. the characterization methodology uses the bufio clock network and idel ay to capture the ddr input registers? edges of operation. th ese measurements do not include package or clock tree skew. s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 60 additional package parameter guidelines the parameters in this section provide the necessary values for calculating timing budgets for pl clock transmitter and receiver data-valid windows. table 84: package skew symbol description devi ce package value units t pkgskew package skew (1) xc7z007s clg225 101 ps clg400 155 ps xc7z012s clg485 182 ps xc7z014s clg400 166 ps clg484 248 ps XC7Z010 clg225 101 ps clg400 155 ps xc7z015 clg485 182 ps xc7z020 clg400 166 ps clg484 248 ps xa7z010 clg225 101 ps clg400 155 ps xa7z020 clg400 166 ps clg484 248 ps xq7z020 cl400 166 ps cl484 248 ps notes: 1. these values represent the worst-case skew between any two selectio resources in the package: shortest delay to longest delay from die pad to ball. 2. package delay information is available for these device/package combinations. this information can be used to deskew the pack age. s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 61 gtp transceiver specifications (onl y available in the xc7z012s and xc7z015) gtp transceiver dc input and output levels table 85 summarizes the dc output specifications of the gtp transceivers in the xc7z012s and xc7z015. consult the 7 series fpgas gtp transceiver user guide ( ug482 ) for further details. note: in figure 21 , differential peak-to-peak voltage = si ngle-ended peak-to-peak voltage x 2. table 85: gtp transceiver dc specifications symbol dc parameter conditions min typ max units dv ppout differential peak-t o-peak output voltage (1) transmitter output swing is set to maximum setting 1000 ? ? mv v cmoutdc dc common mode output voltage equation based v mgtavtt ?dv ppout /4 mv r out differential output resistance ? 100 ? v cmoutac common mode output voltage: ac coupled 1/2 v mgtavtt mv t oskew transmitter output pair (txp and txn) intra-pair skew ? ? 12 ps dv ppin differential peak-to-peak input voltage external ac coupled 150 ? 2000 mv v in single-ended input voltage (2) dc coupled v mgtavtt = 1.2v ?200 ? v mgtavtt mv v cmin common mode input voltage dc coupled v mgtavtt = 1.2v ? 2/3 v mgtavtt ?mv r in differential input resistance ? 100 ? c ext recommended external ac coupling capacitor (3) ? 100 ? nf notes: 1. the output swing and preemphasis levels are programmable using the attributes discussed in the 7 series fpgas gtp transceiver user guide ( ug482 ) and can result in values lower than reported in this table. 2. voltage measured at the pin referenced to gnd. 3. other values can be used as appropriate to conform to specific protocols and standards. x-ref target - figure 20 figure 20: single-ended peak-to-peak voltage x-ref target - figure 21 figure 21: differential peak-to-peak voltage 0 +v p n d s 1 8 7_17_070 3 14 s ingle-ended pe a k-to-pe a k volt a ge 0 +v ?v p?n d s 1 8 7_1 8 _070 3 14 differenti a l pe a k-to-pe a k volt a ge s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 62 table 86 summarizes the dc specifications of the cl ock input of the gtp transceiver. consult the 7 series fpgas gtp transceiver user guide ( ug482 ) for further details. gtp transceiver switching characteristics consult the 7 series fpgas gtp transceiver user guide ( ug482 ) for further information. table 86: gtp transceiver clock dc input level specification symbol dc parameter min typ max units v idiff differential peak-to-peak input voltage 350 ? 2000 mv r in differential input resistance ? 100 ? c ext required external ac coupling capacitor ? 100 ? nf table 87: gtp transceiver performance symbol description output divider speed grade units -3 -2 -1c/-1i/-1li -1q f gtpmax maximum gtp transceiver data rate 6.25 6.25 3.75 n/a gb/s f gtpmin minimum gtp transceiver data rate 0.500 0.500 0.500 n/a gb/s f gtprange pll line rate range 1 3.2?6.25 3.2?6.25 3.2?3.75 n/a gb/s 2 1.6?3.3 1.6?3.3 1.6?3.2 n/a gb/s 4 0.8?1.65 0.8?1.65 0.8?1.6 n/a gb/s 8 0.5?0.825 0.5?0.825 0.5?0.8 n/a gb/s f gtppllrange gtp transceiver pll frequency range 1.6?3.3 1.6?3.3 1.6?3.3 n/a ghz table 88: gtp transceiver dynamic reconfiguration port (drp) switching characteristics symbol description speed grade units -3 -2 -1c/-1i/-1li -1q f gtpdrpclk gtpdrpclk maximum frequency 175 175 156 n/a mhz table 89: gtp transceiver reference clock switching characteristics symbol description conditions all speed grades units min typ max f gclk reference clock frequency range 60 ? 660 mhz t rclk reference clock rise time 20% ? 80% ? 200 ? ps t fclk reference clock fall time 80% ? 20% ? 200 ? ps t dcref reference clock duty cycle tr ansceiver pll only 40 ? 60 % x-ref target - figure 22 figure 22: reference clock ti ming parameters d s 1 8 7_19_0 8 151 3 8 0 % 20 % t fclk t rclk s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 63 table 90: gtp transceiver pll/lock time adaptation symbol description conditions all speed grades units min typ max t lock initial pll lock ? ? 1 ms t dlock clock recovery phase acquisition and adaptation time. after the pll is locked to the reference clock, this is the time it takes to lock the clock data recovery (cdr) to the data present at the input. ? 50,000 2.3 x10 6 ui table 91: gtp transceiver user clock switching characteristics (1) symbol description conditions speed grade units -3 -2 -1c/-1i/-1li -1q f txout txoutclk maximum frequency 390.625 390.625 234.375 n/a mhz f rxout rxoutclk maximum frequency 390.625 390.625 234.375 n/a mhz f txin txusrclk maximum frequency 16-bit data path 390.625 390.625 234.375 n/a mhz f rxin rxusrclk maximum frequency 16-bit data path 390.625 390.625 234.375 n/a mhz f txin2 txusrclk2 maximum frequency 16-bi t data path 390.625 390.625 234.375 n/a mhz f rxin2 rxusrclk2 maximum frequency 16-bit data path 390.625 390.625 234.375 n/a mhz notes: 1. clocking must be implemented as described in the 7 series fpgas gtp transceiver user guide ( ug482 ). s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 64 table 92: gtp transceiver transmitter switching characteristics symbol description cond ition min typ max units f gtptx serial data rate range 0.500 ? f gtpmax gb/s t rtx tx rise time 20%?80% ? 50 ? ps t ftx tx fall time 80%?20% ? 50 ? ps t llskew tx lane-to-lane skew (1) ? ? 500 ps v txoobvdpp electrical idle amplitude ? ? 20 mv t txoobtransition electrical idle transition time ? ? 140 ns tj 6.25 total jitter (2)(3) 6.25 gb/s ? ? 0.30 ui dj 6.25 deterministic jitter (2)(3) ? ? 0.15 ui tj 5.0 total jitter (2)(3) 5.0 gb/s ? ? 0.30 ui dj 5.0 deterministic jitter (2)(3) ? ? 0.15 ui tj 4.25 total jitter (2)(3) 4.25 gb/s ? ? 0.30 ui dj 4.25 deterministic jitter (2)(3) ? ? 0.15 ui tj 3.75 total jitter (2)(3) 3.75 gb/s ? ? 0.30 ui dj 3.75 deterministic jitter (2)(3) ? ? 0.15 ui tj 3.2 total jitter (2)(3) 3.20 gb/s (4) ??0.2ui dj 3.2 deterministic jitter (2)(3) ??0.1ui tj 3.2l total jitter (2)(3) 3.20 gb/s (5) ? ? 0.32 ui dj 3.2l deterministic jitter (2)(3) ? ? 0.16 ui tj 2.5 total jitter (2)(3) 2.5 gb/s (6) ? ? 0.20 ui dj 2.5 deterministic jitter (2)(3) ? ? 0.08 ui tj 1.25 total jitter (2)(3) 1.25 gb/s (7) ? ? 0.15 ui dj 1.25 deterministic jitter (2)(3) ? ? 0.06 ui tj 500 total jitter (2)(3) 500 mb/s ??0.1ui dj 500 deterministic jitter (2)(3) ? ? 0.03 ui notes: 1. using same refclk input with tx phase alignment enabled for up to four consecutive transmitters (one fully populated gtp quad ). 2. using pll[0/1]_fbdiv = 2, 20-bit internal data width. these values are not intended for protocol specific compliance determinat ions. 3. all jitter values are based on a bit-error ratio of 1e -12 . 4. pll frequency at 3.2 ghz and txout_div = 2. 5. pll frequency at 1.6 ghz and txout_div = 1. 6. pll frequency at 2.5 ghz and txout_div = 2. 7. pll frequency at 2.5 ghz and txout_div = 4. s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 65 table 93: gtp transceiver receiver switching characteristics symbol description min typ max units f gtprx serial data rate rx oversampler not enabled 0.500 ? f gtpmax gb/s t rxelecidle time for rxelecidle to respond to loss or restoration of data ? 10 ? ns rx oobvdpp oob detect threshold peak-to-peak 60 ? 150 mv rx sst receiver spread-spectrum tracking (1) modulated @ 33 khz ?5000 ? 5000 ppm rx rl run length (cid) ? ? 512 ui rx ppmtol data/refclk ppm offset tolerance ?1250 ? 1250 ppm sj jitter tolerance (2) jt_sj 6.25 sinusoidal jitter (3) 6.25 gb/s 0.44 ? ? ui jt_sj 5.0 sinusoidal jitter (3) 5.0 gb/s 0.44 ? ? ui jt_sj 4.25 sinusoidal jitter (3) 4.25 gb/s 0.44 ? ? ui jt_sj 3.75 sinusoidal jitter (3) 3.75 gb/s 0.44 ? ? ui jt_sj 3.2 sinusoidal jitter (3) 3.2 gb/s (4) 0.45 ? ? ui jt_sj 3.2l sinusoidal jitter (3) 3.2 gb/s (5) 0.45 ? ? ui jt_sj 2.5 sinusoidal jitter (3) 2.5 gb/s (6) 0.5 ? ? ui jt_sj 1.25 sinusoidal jitter (3) 1.25 gb/s (7) 0.5 ? ? ui jt_sj 500 sinusoidal jitter (3) 500 mb/s 0.4 ? ? ui sj jitter tolerance with stressed eye (2) jt_tjse 3.2 total jitter with stressed eye (8) 3.2 gb/s 0.70 ? ? ui jt_tjse 6.25 6.25 gb/s 0.70 ? ? ui jt_sjse 3.2 sinusoidal jitter with stressed eye (8) 3.2 gb/s 0.1 ? ? ui jt_sjse 6.25 6.25 gb/s 0.1 ? ? ui notes: 1. using rxout_div = 1, 2, and 4. 2. all jitter values are based on a bit error ratio of 1e ?12 . 3. the frequency of the injected sinusoidal jitter is 10 mhz. 4. pll frequency at 3.2 ghz and rxout_div = 2. 5. pll frequency at 1.6 ghz and rxout_div = 1. 6. pll frequency at 2.5 ghz and rxout_div = 2. 7. pll frequency at 2.5 ghz and rxout_div = 4. 8. composite jitter. s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 66 gtp transceiver protocol jitter characteristics for table 94 through table 98 , the 7 series fpgas gtp transceiver user guide ( ug482 ) contains recommended settings for optimal usage of protocol specific characteristics. table 94: gigabit ethernet protocol characteristics description line rate (mb/s) min max units gigabit ethernet transmitter jitter generation total transmitter jitter (t_tj) 1250 ? 0.24 ui gigabit ethernet receiver high frequency jitter tolerance total receiver jitter tolerance 1250 0.749 ? ui table 95: xaui protocol characteristics description line rate (mb/s) min max units xaui transmitter jitter generation total transmitter jitter (t_tj) 3125 ? 0.35 ui xaui receiver high freq uency jitter tolerance total receiver jitter tolerance 3125 0.65 ? ui table 96: pci express protocol characteristics (1) standard description line rate (mb/s) min max units pci express transmitter jitter generation pci express gen 1 total transmitter jitter 2500 ? 0.25 ui pci express gen 2 total transmitter jitter 5000 ? 0.25 ui pci express receiver high frequency jitter tolerance pci express gen 1 total receiver jitter tolerance 2500 0.65 ? ui pci express gen 2 (2) receiver inherent timing error 5000 0.40 ? ui receiver inherent deterministic timing error 0.30 ? ui notes: 1. tested per card electromechanical (cem) methodology. 2. using common refclk. table 97: cei-6g protocol characteristics description line rate (m b/s) interface min max units cei-6g transmitter jitter generation total transmitter jitter (1) 4976?6375 cei-6g-sr ? 0.3 ui cei-6g receiver high fr equency jitter tolerance total receiver jitter tolerance (1) 4976?6375 cei-6g-sr 0.6 ? ui notes: 1. tested at most commonly used line rate of 6250 mb/s using 390.625 mhz reference clock. s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 67 integrated interface block for pci express de signs switching characteristics (xc7z012s and xc7z015 only) this block is only available in the xc7z012s and xc7z015. mo re information and do cumentation on soluti ons for pci express designs can be found at: www.xilinx.com/technology/p rotocols/pciexpress.htm . table 98: cpri protocol characteristics description line rate (mb/s) min max units cpri transmitter jitter generation total transmitter jitter 614.4 ? 0.35 ui 1228.8 ? 0.35 ui 2457.6 ? 0.35 ui 3072.0 ? 0.35 ui 4915.2 ? 0.3 ui 6144.0 ? 0.3 ui cpri receiver frequency jitter tolerance total receiver jitter tolerance 614.4 0.65 ? ui 1228.8 0.65 ? ui 2457.6 0.65 ? ui 3072.0 0.65 ? ui 4915.2 (1) 0.60 ? ui 6144.0 (1) 0.60 ? ui notes: 1. tested to cei-6g-sr. table 99: maximum performance for pci express designs (xc7z012s and xc7z015 only) symbol description speed grade units -3 -2 -1c/-1i/-1li -1q f pipeclk pipe clock maximum frequency 250.00 250.00 250.00 n/a mhz f userclk user clock maximum frequency 250.00 250.00 250.00 n/a mhz f userclk2 user clock 2 maximum frequency 250.00 250.00 250.00 n/a mhz f drpclk drp clock maximum frequency 250.00 250.00 250.00 n/a mhz notes: 1. refer to the 7 series fpgas integrated block for pci express product guide ( pg054 ) for specific supported core configurations. s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 68 xadc specifications table 100: xadc specifications parameter symbol comments/conditions min typ max units v ccadc = 1.8v 5%, v refp = 1.25v, v refn = 0v, adcclk = 26 mhz, ?55c t j 125c, typical values at t j =+40c adc accuracy (1) resolution 12 ? ? bits integral nonlinearity (2) inl ?40c t j 100c ? ? 2 lsbs ?55c t j < ?40c; 100c < t j 125c ? ? 3 lsbs differential nonlinearity dnl no missing codes, guaranteed monotonic ? ? 1 lsbs offset error unipolar ?40c t j 100c ? ? 8 lsbs ?55c t j < ?40c; 100c < t j 125c 12 lsbs bipolar ?55c t j 125c ? ? 4 lsbs gain error ??0.5% offset matching ? ? 4 lsbs gain matching ??0.3 % sample rate ?? 1ms/s signal to noise ratio (2) snr f sample = 500ks/s, f in = 20khz 60 ? ? db rms code noise external 1.25v reference ? ? 2 lsbs on-chip reference ? 3 ? lsbs total harmonic distortion (2) thd f sample = 500ks/s, f in = 20khz 70 ? ? db analog inputs (3) adc input ranges unipolar operation 0 ? 1 v bipolar operation ?0.5 ? +0.5 v unipolar common mode range (fs input) 0 ? +0.5 v bipolar common mode range (fs input) +0.5 ? +0.6 v maximum external channel input ranges adjacent analog channels set within these ranges should not corrupt measurements on adjacent channels ?0.1 ? v ccadc v auxiliary channel full resolution bandwidth frbw 250 ? ? khz on-chip sensors temperature sensor error ?40c t j 100c ? ? 4 c ?55c t j < ?40c; 100c < t j 125c ? ? 6 c supply sensor error ?40c t j 100c ? ? 1 % ?55c t j < ?40c; 100c < t j 125c ? ? 2 % conversion rate (4) conversion time - continuous t conv number of adcclk cycles 26 ? 32 cycles conversion time - event t conv number of clk cycles ? ? 21 cycles drp clock frequency dclk drp clock frequency 8 ? 250 mhz adc clock frequency adcclk derived from dclk 1 ? 26 mhz dclk duty cycle 40 ? 60 % s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 69 configuration switching characteristics xadc reference (5) external reference v refp externally supplied reference voltage 1.20 1.25 1.30 v on-chip reference ground v refp pin to agnd, ?40c t j 100c 1.2375 1.25 1.2625 v ground v refp pin to agnd, ?55c t j < ?40c; 100c < t j 125c 1.225 1.25 1.275 v notes: 1. offset and gain errors are removed by enabling the xadc automatic gain calibration feature. the values are specified for when this feature is enabled. 2. only specified for bitstream option xadcenhancedlinearity = on. 3. see the adc chapter in the 7 series fpgas and zynq-7000 all progr ammable soc xadc dual 12-bit 1 msps analog-to-digital converter user guide ( ug480 ) for a detailed description. 4. see the timing chapter in the 7 series fpgas and zynq-7000 all programmable soc xadc dual 12-bit 1 msps analog-to-digital converter user guide ( ug480 ) for a detailed description. 5. any variation in the reference voltage from the nominal v refp = 1.25v and v refn = 0v will result in a deviation from the ideal transfer function. this also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). however, for external ratiometric type applications allowing reference to vary by 4% is permitted. table 101: configuration switching characteristics symbol description speed grade units -3 -2 -1c/-1i/-1li -1q power-up timing characteristics t pl (1) program latency 5.00 5.00 5.00 5.00 ms, max t por power-on reset (50 ms ramp ra te time) 10/50 10/50 10/50 10/50 ms, min/max power-on reset (1 ms ramp rate time) with the power-on reset override function disabled; ( devcfg.ctrl.pcfg_por_cnt_4k = 0 ). (2) 10/35 10/35 10/35 10/35 ms, min/max power-on reset (1 ms ramp rate time) with the power-on reset override function enabled; ( devcfg.ctrl.pcfg_por_cnt_4k = 1 ). (2) 2/8 2/8 2/8 2/8 ms, min/max t program program pulse width 250.00 250.00 250.00 250.00 ns, min boundary-scan port timing specifications t taptck /t tcktap tms and tdi setup/hold 3.00/2.00 3. 00/2.00 3.00/2.00 3.00/2.00 ns, min t tcktdo tck falling edge to tdo output 7.00 7.00 7.00 7.00 ns, max f tck tck frequency 66.00 66.00 66.00 66.00 mhz, max internal configuration access port f icapck internal configuration access port (icape2) 100.00 100.00 100.00 100.00 mhz, max device dna access port f dnack dna access port (dna_port) 100.00 100.00 100.00 100.00 mhz, max notes: 1. to support longer delays in configuration, use the design solutions described in the 7 series fpga configuration user guide ( ug470 ). 2. for non-secure boot only. measurement is made when the ps is already powered and stable, before power cycling the pl. table 100: xadc specifications (cont?d) parameter symbol comments/conditions min typ max units s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 70 efuse programming conditions table 102 lists the programming conditions specifically for efuse. for more information, see the 7 series fpga configuration user guide ( ug470 ). revision history the following table shows the revi sion history for this document: table 102: efuse programming conditions (1) symbol description min typ max units i plfs pl v ccaux supply current ? ? 115 ma i psfs ps v ccpaux supply current ? ? 115 ma t j temperature range 15 ? 125 c notes: 1. the zynq-7000 device must not be configured during efuse programming. date version description of revisions 05/07/2012 1.0 initial xilinx release. 06/27/2012 1.1 updated the descriptions, changed v in , note 3 , note 4 , and added v pref , v pin , and note 5 in table 1 . in table 2 , updated descriptions and notes. updated table 3 and added r in_term . removed i ccmioq from table 5 . removed i ccmioq and updated xc7z020 in table 6 . updated lvcmos12, sstl135, and sstl15 in table 10 . updated table 18 . in ps performance characteristics section, added timing diagrams and revised many tables. updated table 50 and removed notes 2 and 3. added note 2 and note 3 to table 51 . changed table 53 by adding t ioibufdisable . removed many of the combinatorial delay specifications and t cinck /t ckcin from table 62 . in table 100 updated offset error and matching descriptions and gain error and matching descriptions, and added note 2 to integral nonlinearity. 09/12/2012 1.2 changed note 3 and added note 5 in table 1 . updated t j in table 2 , also revised note 4 and note 9 . updated specifications including r in_term in table 3 . added table 4 . updated the xc7z020 specifications in table 6 . updated standards in table 8 . updated specifications in table 12 . updated the ac switching characteristics section for the ise tools 14.2 speed specifications throughout the document. in ps performance characteristics section introduction, revised tables, updated figure 4, and added figure 5. updated parameters in figure 6 through figure 13. updated values in table 17 . added note 2 to table 23. added note 3 to table 36 . updated descriptions and revised f mspiclk in table 41 . updated note 3 in table 51 . changed f pfdmax conditions in table 72 and table 73 . updated devices and added values to table 84 . 02/11/2013 1.3 updated the ac switching characteristics based upon ise tools 14.4 and vivado tools 2012.4, both at v1.05 for the -3, -2, and -1 speed specif ications throughout the document. updated table 15 and table 16 to the product status of production for the xc7z020 devices with -2 and -1 speed specifications. updated description in introduction . revised v pin in table 1 . revised v pin and i in and added note 2 to table 2 . clarified ps specifications, added c pin , and removed note 3 on i rpd in table 3 . added values to table 5 . updated power supply requirements section. revised descriptions in table 7 . revised note 1 , removed lvttl, notes 2 and 3, and added sstl135 to table 8 . added table 9 . removed hstl_i_12 and sstl_12 from table 10 . removed diff_sstl12 from table 12 . revise in v cco min/max in table 13 . many changes to the ps switching characteristics section including adding tables, figures, notes with test conditions where applicable. in table 17 , updated the 6:2:1 clock ratio frequencies. updated minimum value for t ulpidck in table 35 . added a 2:1 memory controller section to table 51 . updated note 1 in table 69 . updated note 1 and note 2 in table 84 .updated the rows on offset error and matching and gain error and matching and the maximum external channel input ranges in table 100 . added internal configuration access port section to table 101 . s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 71 02/14/2013 1.4 corrected t qspickd2 minimum equation in table 34 . updated timing parameter names in figure 4 and figure 5 to match those in the accompanying table. 02/19/2013 1.4.1 corrected version history. 03/19/2013 1.5 updated table 15 and table 16 to the product status of production for the XC7Z010 devices with -2 and -1 speed specifications. updated figure 4 by adding out0. added note 2 to table 33 . added table 38 and figure 9 . 04/24/2013 1.6 all the devices listed in this data sheet are production released. updated the ac switching characteristics based upon ise tools 14.5 and vivado tools 2013.1, both at v1.06 for the -3, -2, and -1 speed specifications throu ghout the document. updated table 15 and table 16 for production release of the XC7Z010 and xc7z020 in the -3 speed designations. removed the ps power-on reset section. updated the ps?pl power sequencing section. in table 1 , revised v in (i/o input voltage) to match values in table 4 , and combined note 4 with old note 5 and then added new note 6 . revised v in description and added note 8 in table 2 . updated first 3 rows in table 4 . revised pci33_3 voltage minimum in table 10 to match values in table 1 and table 4 . added note 1 to table 13 . clarified the load conditions in table 34 by adding new data. clarified title of table 51 . throughout the data sheet ( table 62 , table 63 , table 64 , and table 79 ) removed the obvious note ?a zero ?0? hold time listing indicates no hold time or a negative hold time.? 07/08/2013 1.7 added note 5 to table 2 . revised the frequency of cpu clock performance (6:2:1) in table 17 . updated f ddr3l_max values in table 18 . moved and added f axi_max to table 19 . updated the minimum t dqvalid values in table 25 and table 26 . in table 37 , corrected the f sdsclk maximum value. in table 38 , corrected f sdsclk and fixed the f sdidclk typographical unit error. values in table 78 and table 82 were reported incorrectly and have been updated to match speed specifications. 09/12/2013 1.8 added the xc7z015 throughout the document. the xc7z015 is the onl y device in this data sheet that includes gtp transceivers. added the gtp transceivers specifications to table 1 , table 2 , and table 7 , and the pl power-on/off power supply sequencing , ps?pl power sequencing , gtp transceiver specifications (only available in the xc7z012s and xc7z015) , integrated interface block for pci express designs switching characteristics (xc7z012s and xc7z015 only) and sections. added usrcclk output section and clarified values for t por in table 101 . added i psfs to table 102 . updated notice of disclaimer . 11/26/2013 1.9 added specifications fo r the xq7z020 with the -1q speed sp ecification/temperature range. added specifications for the xa7z010 and xa7z020 with the -1q speed s pecification/temperature range. removed note 1 and note 2 from table 6 . added table 14 . updated table 100 specifications. in table 101 , removed the usrcclk output section, added t pl , t program , note 1 , and the device dna access port section, and updated the t por description. 01/20/2014 1.10 update note 7 in table 2 . added note 2 to table 4 . updated speed files in data sheet and table 14 . updated table 15 and table 16 for production release of the xa7z010 and xa7z020 in the -1i and -1q speed designations. added i/o standards to table 52 and improved all of the t iotp speed specifications. 02/25/2014 1.11 production release of t he xc7z015 for all speed specifications and temperature ranges, including finalizing information in table 15 and table 16 . added xc7z015 data to table 5 , table 6 , and table 71 . added table 27 . 07/14/2014 1.12 in table 4 , updated note 2 per the customer notice 7 series fpga and zynq-7000 ap soc i/o undershoot voltage data sheet update ( xcn14014 ). added heading lvds dc specifications (lvds_25) . fixed units for t dqss in table 27 . updated heading input/output delay switching characteristics . updated f idelayctrl_ref , t idelaypat_jit and t odelaypat_jit , and note 1 in table 60 . removed note from table 62 . updated description of t ickof and added note 2 to table 74 . updated description of t ickoffar and added note 2 to table 75 . revised dv ppout and v in , and added note 2 to table 85 . revised labels in figure 20 and figure 21 and added a note after figure 21 . added note 1 to table 99 . 10/09/2014 1.13 added -1li sp eed grade throughout. updated introduction . removed 3.3v as descriptor of hr i/o banks throughout. in pl power-on/off power supply sequencing , added sentence about there being no recommended sequence for supplies not shown. in ps?pl power sequencing , removed list of pl power supplies. in table 20 , removed typical value and added maximum value for t rfpsclk . added note about measurement being taken from v ref to v ref in table 25 to table 32 . added i/o standard adjustment measurement methodology . date version description of revisions s e n d f e e d b a c k
zynq-7000 all programmable soc (z-7007s, z-7012s, z-7014s, z-7010, z-7015, and z-7020) ds187 (v1.19) october 3, 2016 www.xilinx.com product specification 72 notice of disclaimer the information disclosed to you hereunder (t he ?materials?) is provided solely for th e selection and use of xilinx products. t o the maximum extent permitted by applicable law: (1) materials are ma de available "as is" and with a ll faults, xilinx hereby disclai ms all warranties and conditions, express, implied, or st atutory, including but not limited to warranties of merchantability, non-infringement, or fitness for any partic ular purpose; and (2) xilinx sh all not be liable (whether in contract or tort, including negligence, or und er any other theory of liability) for any loss or damage of any kind or nature re lated to, arising under, or in connection with, the materials (including your use of the materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reas onably foreseeable or xilinx had been advised of the possibility of the same. xilinx assumes no obligation to correct any errors contained in the materials or to not ify you of updates to the materials or t o product specifications. you may not reproduce, modif y, distribute, or publicly display the ma terials without prior written consent. cer tain products are subject to the terms and conditions of xilinx?s limited warrant y, please refer to xilinx?s terms of sale which can be viewe d at www.xilinx.com/legal.htm#tos ; ip cores may be subject to warranty and support terms contained in a license issued to you by xilinx. xilinx products are not designed or in tended to be fail-safe or for use in any applic ation requiring fail-safe performance; you assume sole risk and liability for use of xilinx products in such critical applic ations, please refer to xilinx?s terms of sale which can be vie wed at www.xilinx.com/legal.htm#tos . automotive applications disclaimer automotive products (identified as ?xa? in the part number) are not warranted for use in the deployment of airbags or for use in applications that affect control of a vehicl e (?safety application?) unless there is a safety concept or redundancy feature consistent with the iso 26262 automoti ve safety standard (?safety design?). customer shall, prior to using or distributing any systems that incorporate products, thoroughly test such systems for safety purposes. use of products in a safety application without a safety design is fully at the risk of customer, subject only to applicable laws and regulations governing limitations on product liability. 11/19/2014 1.14 added v ccbram to introduction . replaced -1l speed grade with -1li and removed 1.0v row for v ccint and v ccbram in table 2 . updated the ac switching characteristics based upon vivado 2014.4. updated vivado software version in table 14 . in table 15 , moved -1li speed grade for XC7Z010, xc7z015, and xc7z020 devices from advance to production. in table 16 , added vivado 2013.1 software version to -2 e, -2i, -1c, and -1i speed grades of XC7Z010 and xc7z020 devices, added vivado 2014.4 software version to -1li speed grade for all commercial devices, and removed table note. added selecting the correct speed grade and voltage in the vivado tools . added note 1 to table 49 . in table 51 , moved lpddr2 row to end of 2: 1 memory controllers section. 02/23/2015 1.15 updated descriptions of v ccpint in table 1 and table 2 . added note 6 to table 11 . in table 13 , changed maximum v icm value from 1.425v to 1.500v. updated table 22 title. added figure 1 and table 23 . in table 34 , updated minimum t qspidck2 and t qspickd2 to 6 ns and 12.5 ns, respectively, and removed note 5. in table 65 , added t rdck_di_eccw /t rckd_di_eccw and t rdck_di_ecc_fifo / t rckd_di_ecc_fifo , updated t rcck_en /t rckc_en symbols, and updated note 1 . in table 66 , updated t dspdck_ { a, b } _mreg_mult /t dspckd_ { a, b}_mreg_mult and t dspdck_ { a, d } _adreg / t dspckd_ { a, d}_adreg symbols, and replaced b input with a input for t dspdo_a_p . removed minimum sample rate specification from table 100 . 09/22/2015 1.16 updated data sheet per the customer notice xcn15034: zynq-7000 ap soc requirement for the ps power-off sequence . assigned quiescent supply currents to -1li speed grade xq7z020 device in table 5 . updated ps power-on/off power supply sequencing . removed n/a from -1li speed gradexq7z020 device production software cell in table 16 . added f smc_ref_clk to table 33 . 11/24/2015 1.17 updated the ac switching characteristics based upon vivado 2015.4. in table 15 , added -1li speed grade to production column for xq7z020. in table 16 , added vivado 2015.4 software version to -1li speed grade column for xq7z020. in figure 4 and figure 5 , added extra clock pulse on qspi_sclk_out. 07/26/2016 1.18 updated first sentence in ps power-on/off power supply sequencing . added t pspor to note 1 in table 22 . in table 54 , changed v meas for lvcmos (3.3v), lvttl (3.3v), and pci33 (3.3v) to 1.65v. 10/03/2016 1.19 added xc7z007s, xc7z012s, and xc7z014s throughout. updated the ac switching characteristics based upon vivado 2016.3. date version description of revisions s e n d f e e d b a c k

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